arm64: dts: qcom: sa8775p: remove aux clock from pcie phy

The gcc_aux_clk is used by the PCIe Root Complex (RC) and is not required
by the PHY. The correct clock for the PHY is gcc_phy_aux_clk, which this
patch uses to replace the incorrect reference.

The distinction between AUX_CLK and PHY_AUX_CLK is important: AUX_CLK is
typically used by the controller, while PHY_AUX_CLK is required by certain
PHYs—particularly Gen4 QMP PHYs—for internal operations such as clock
gating and power management. Some non-Gen4 Qualcomm PHYs also use
PHY_AUX_CLK, but they do not require AUX_CLK.

This change ensures proper clock configuration and avoids unnecessary
dependencies.

Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250725102231.3608298-3-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 322abd0294be74386fa47b45b6a5e6f4caa666cb..4ccaddb7794c1e3ba5e243ecacbfb95e7b1d8b9c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -7719,16 +7719,18 @@
                compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
                reg = <0x0 0x1c04000 0x0 0x2000>;
 
-               clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+               clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
                         <&gcc GCC_PCIE_CLKREF_EN>,
                         <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
                         <&gcc GCC_PCIE_0_PIPE_CLK>,
-                        <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
-                        <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
-
-               clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
-                             "pipediv2", "phy_aux";
+                        <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
+               clock-names = "aux",
+                             "cfg_ahb",
+                             "ref",
+                             "rchng",
+                             "pipe",
+                             "pipediv2";
 
                assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
                assigned-clock-rates = <100000000>;
@@ -7885,16 +7887,18 @@
                compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
                reg = <0x0 0x1c14000 0x0 0x4000>;
 
-               clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+               clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
                         <&gcc GCC_PCIE_CLKREF_EN>,
                         <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
                         <&gcc GCC_PCIE_1_PIPE_CLK>,
-                        <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
-                        <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
-
-               clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
-                             "pipediv2", "phy_aux";
+                        <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
+               clock-names = "aux",
+                             "cfg_ahb",
+                             "ref",
+                             "rchng",
+                             "pipe",
+                             "pipediv2";
 
                assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
                assigned-clock-rates = <100000000>;