FLAG( 6, 0, ECX, 1, 1, ACNT2, ANY, 13, FALSE) \
FLAG( 6, 0, ECX, 3, 1, ENERGY_PERF_BIAS, NO, 0, FALSE)
+#if defined (COMMUNITY_SOURCE_INTEL_SECRET) || \
+ defined (COMMUNITY_SOURCE_AMD_SECRET) /* { */
+/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV, CPL3 */
+#define CPUID_7_EDX_26 \
+FLAG( 7, 0, EDX, 26, 1, IBRSIBPB, YES, 9, FALSE)
+#define CPUID_7_EDX_27 \
+FLAG( 7, 0, EDX, 27, 1, STIBP, YES, 9, FALSE)
+#else
+#define CPUID_7_EDX_26 \
+FLAG( 7, 0, EDX, 26, 1, LEVEL7EDX_RSVD1, NO, 0, FALSE)
+#define CPUID_7_EDX_27 \
+FLAG( 7, 0, EDX, 27, 1, LEVEL7EDX_RSVD2, NO, 0, FALSE)
+#endif /* } COMMUNITY_SOURCE_INTEL_SECRET || COMMUNITY_SOURCE_AMD_SECRET */
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV, CPL3 */
#define CPUID_FIELD_DATA_LEVEL_7 \
FLAG( 7, 0, ECX, 22, 1, RDPID, NO, 0, TRUE) \
FLAG( 7, 0, ECX, 30, 1, SGX_LC, NO, 0, FALSE) \
FLAG( 7, 0, EDX, 2, 1, AVX512QVNNIW, YES, 15, TRUE) \
-FLAG( 7, 0, EDX, 3, 1, AVX512QFMAPS, YES, 15, TRUE)
-
+FLAG( 7, 0, EDX, 3, 1, AVX512QFMAPS, YES, 15, TRUE) \
+CPUID_7_EDX_26 \
+CPUID_7_EDX_27
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV, CPL3 */
#define CPUID_FIELD_DATA_LEVEL_A \
FLAG( 87, 0, EDX, 8, 1, TSC_INVARIANT, NA, 0, FALSE) \
FLAG( 87, 0, EDX, 9, 1, CORE_PERF_BOOST, NA, 0, FALSE)
+#define CPUID_88_EBX_12 \
+FLAG( 88, 0, EBX, 12, 1, LEVEL88EBX_RSVD1, NO, 0, FALSE)
+
/* LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV, CPL3 */
#define CPUID_FIELD_DATA_LEVEL_88 \
FIELD( 88, 0, EAX, 0, 8, PHYS_BITS, YES, 4, FALSE) \
FLAG( 88, 0, EBX, 0, 1, CLZERO, YES, 14, TRUE) \
FLAG( 88, 0, EBX, 1, 1, IRPERF, NO, 0, FALSE) \
FLAG( 88, 0, EBX, 2, 1, XSAVE_ERR_PTR, NO, 0, FALSE) \
+CPUID_88_EBX_12 \
FIELD( 88, 0, ECX, 0, 8, LEAF88_CORE_COUNT, YES, 4, FALSE) \
FIELD( 88, 0, ECX, 12, 4, APICID_COREID_SIZE, YES, 7, FALSE) \
FIELD( 88, 0, ECX, 16, 2, PERFTSC_SIZE, NO, 0, FALSE)