RISC-V: Allow RVV register overlap for v[sz]ext.vf8

Like v[sz]ext.vf4, allow the rvv register overlap
for v[sz]ext.vf8.

gcc/ChangeLog:

	* config/riscv/vector.md: Leverage Wvr constraint.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index a5ebc85b764e7cd4a1d84fe3143db21d3595d9df..dca6108e0aaa260b20711dfd2270c04186a41e17 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4130,19 +4130,19 @@
 
 ;; Vector Oct-Widening Sign-extend and Zero-extend.
 (define_insn "@pred_<optab><mode>_vf8"
-  [(set (match_operand:VOEXTI 0 "register_operand"         "=&vr,&vr")
+  [(set (match_operand:VOEXTI 0 "register_operand"            "=vr,  vr,  vd,  vd")
        (if_then_else:VOEXTI
          (unspec:<VM>
-           [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
-            (match_operand 4 "vector_length_operand"         "  rvl,  rvl")
-            (match_operand 5 "const_int_operand"             "    i,    i")
-            (match_operand 6 "const_int_operand"             "    i,    i")
-            (match_operand 7 "const_int_operand"             "    i,    i")
+           [(match_operand:<VM> 1 "vector_mask_operand"      "Wc1, Wc1,  vm,  vm")
+            (match_operand 4 "vector_length_operand"         "rvl, rvl, rvl, rvl")
+            (match_operand 5 "const_int_operand"             "  i,   i,   i,   i")
+            (match_operand 6 "const_int_operand"             "  i,   i,   i,   i")
+            (match_operand 7 "const_int_operand"             "  i,   i,   i,   i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (any_extend:VOEXTI
-           (match_operand:<V_OCT_TRUNC> 3 "register_operand" "   vr,   vr"))
-         (match_operand:VOEXTI 2 "vector_merge_operand"      "   vu,    0")))]
+           (match_operand:<V_OCT_TRUNC> 3 "register_operand" "Wvr, Wvr, Wvr, Wvr"))
+         (match_operand:VOEXTI 2 "vector_merge_operand"      " vu,   0,  vu,   0")))]
   "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "v<sz>ext.vf8\t%0,%3%p1"
   [(set_attr "type" "vext")