]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu: add wrapper functions for pmfw eeprom interface
authorGangliang Xie <ganglxie@amd.com>
Mon, 15 Sep 2025 09:13:25 +0000 (17:13 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 4 Nov 2025 16:53:58 +0000 (11:53 -0500)
add wrapper functions for pmfw eeprom interface, for these interfaces
to be easily and safely called

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h

index 89d0def82797d938d1d0a024a15709031fbfbb8f..258ff0f121a29fd04e13c68b06d7307e04f9e86f 100644 (file)
@@ -1609,3 +1609,101 @@ bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev)
 
        return !!(flags & RAS_SMU_FEATURE_BIT__RAS_EEPROM);
 }
+
+int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev,
+                                    uint32_t *table_version)
+{
+       const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);
+
+       if (!amdgpu_ras_smu_eeprom_supported(adev))
+               return -EOPNOTSUPP;
+
+       if (smu_ras_drv->smu_eeprom_funcs->get_ras_table_version)
+               return smu_ras_drv->smu_eeprom_funcs->get_ras_table_version(adev,
+                                                                                table_version);
+       return -EOPNOTSUPP;
+}
+
+int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev,
+                                    uint32_t *count, uint32_t timeout)
+{
+       const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);
+
+       if (!amdgpu_ras_smu_eeprom_supported(adev))
+               return -EOPNOTSUPP;
+
+       if (smu_ras_drv->smu_eeprom_funcs->get_badpage_count)
+               return smu_ras_drv->smu_eeprom_funcs->get_badpage_count(adev,
+                                                                            count, timeout);
+       return -EOPNOTSUPP;
+}
+
+int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev,
+                                       uint16_t index, uint64_t *mca_addr)
+{
+       const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);
+
+       if (!amdgpu_ras_smu_eeprom_supported(adev))
+               return -EOPNOTSUPP;
+
+       if (smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr)
+               return smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr(adev,
+                                                                               index, mca_addr);
+       return -EOPNOTSUPP;
+}
+
+int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev,
+                                uint64_t timestamp)
+{
+       const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);
+
+       if (!amdgpu_ras_smu_eeprom_supported(adev))
+               return -EOPNOTSUPP;
+
+       if (smu_ras_drv->smu_eeprom_funcs->set_timestamp)
+               return smu_ras_drv->smu_eeprom_funcs->set_timestamp(adev,
+                                                                        timestamp);
+       return -EOPNOTSUPP;
+}
+
+int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev,
+                                uint16_t index, uint64_t *timestamp)
+{
+       const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);
+
+       if (!amdgpu_ras_smu_eeprom_supported(adev))
+               return -EOPNOTSUPP;
+
+       if (smu_ras_drv->smu_eeprom_funcs->get_timestamp)
+               return smu_ras_drv->smu_eeprom_funcs->get_timestamp(adev,
+                                                                        index, timestamp);
+       return -EOPNOTSUPP;
+}
+
+int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev,
+                                   uint16_t index, uint64_t *ipid)
+{
+       const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);
+
+       if (!amdgpu_ras_smu_eeprom_supported(adev))
+               return -EOPNOTSUPP;
+
+       if (smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid)
+               return smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid(adev,
+                                                                           index, ipid);
+       return -EOPNOTSUPP;
+}
+
+int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev,
+                                  uint32_t *result)
+{
+       const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);
+
+       if (!amdgpu_ras_smu_eeprom_supported(adev))
+               return -EOPNOTSUPP;
+
+       if (smu_ras_drv->smu_eeprom_funcs->erase_ras_table)
+               return smu_ras_drv->smu_eeprom_funcs->erase_ras_table(adev,
+                                                                          result);
+       return -EOPNOTSUPP;
+}
index feff46b22b6ff5e7736cb174a67886fb48268d76..cfbd402ddea2f3f9cf8ba9a6d69933873de82326 100644 (file)
@@ -165,6 +165,27 @@ void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev);
 
 bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev);
 
+int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev,
+                                                       uint32_t *table_version);
+
+int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev,
+                                                               uint32_t *count, uint32_t timeout);
+
+int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev,
+                                                               uint16_t index, uint64_t *mca_addr);
+
+int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev,
+                                                                               uint64_t timestamp);
+
+int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev,
+                                                       uint16_t index, uint64_t *timestamp);
+
+int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev,
+                                                               uint16_t index, uint64_t *ipid);
+
+int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev,
+                                                                       uint32_t *result);
+
 extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops;
 extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops;