u32 val;
cdclk_config->vco = vlv_get_hpll_vco(display->drm);
- cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk",
- CCK_DISPLAY_CLOCK_CONTROL,
- cdclk_config->vco);
+ cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm);
vlv_punit_get(display->drm);
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
return i915->czclk_freq;
}
+int vlv_clock_get_cdclk(struct drm_device *drm)
+{
+ return vlv_get_cck_clock(drm, "cdclk", CCK_DISPLAY_CLOCK_CONTROL,
+ vlv_get_hpll_vco(drm));
+}
+
int vlv_clock_get_gpll(struct drm_device *drm)
{
return vlv_get_cck_clock(drm, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
const char *name, u32 reg, int ref_freq);
int vlv_clock_get_hrawclk(struct drm_device *drm);
int vlv_clock_get_czclk(struct drm_device *drm);
+int vlv_clock_get_cdclk(struct drm_device *drm);
int vlv_clock_get_gpll(struct drm_device *drm);
bool intel_has_pending_fb_unpin(struct intel_display *display);
void intel_encoder_destroy(struct drm_encoder *encoder);