clk: rockchip: fix rk3188 sclk_smc gate data

[ Upstream commit a9f0c0e563717b9f63b3bb1c4a7c2df436a206d9 ]

Fix sclk_smc gate data.
Change variable order, flags come before the register address.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx9999@hotmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 69fb3afc970fb5d94aebfa7825e71443304c6955..9a6ad5a4cdf06218180cdbb2f8df9dbfd8e938e4 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -391,8 +391,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         * Clock-Architecture Diagram 4
         */
 
-       GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
-                       RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
+       GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
+                       RK2928_CLKGATE_CON(2), 4, GFLAGS),
 
        COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
                        RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,