intel_idle: Add Panther Lake C-states table

Panther Lake supports the following requestable C-states: C1, C1E, C6S,
C10.

The parameters of these C-states should be consistent across all
systems based on Panther Lake, so add a custom C-states table for it
that will override C-state parameters supplied by platform firmware
that may vary from one platform to another and may not represent the
most optimum choice.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
[ rjw: Changelog expansion ]
Link: https://patch.msgid.link/20260309083818.79588-1-dedekind1@gmail.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index f49c939d636f489791386704a3d1455147fd28f3..f49354e3777779597c0bab38bd0d0de3ed6a09fa 100644 (file)
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -983,6 +983,43 @@ static struct cpuidle_state mtl_l_cstates[] __initdata = {
                .enter = NULL }
 };
 
+static struct cpuidle_state ptl_cstates[] __initdata = {
+       {
+               .name = "C1",
+               .desc = "MWAIT 0x00",
+               .flags = MWAIT2flg(0x00),
+               .exit_latency = 1,
+               .target_residency = 1,
+               .enter = &intel_idle,
+               .enter_s2idle = intel_idle_s2idle, },
+       {
+               .name = "C1E",
+               .desc = "MWAIT 0x01",
+               .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
+               .exit_latency = 10,
+               .target_residency = 10,
+               .enter = &intel_idle,
+               .enter_s2idle = intel_idle_s2idle, },
+       {
+               .name = "C6S",
+               .desc = "MWAIT 0x21",
+               .flags = MWAIT2flg(0x21) | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 300,
+               .target_residency = 300,
+               .enter = &intel_idle,
+               .enter_s2idle = intel_idle_s2idle, },
+       {
+               .name = "C10",
+               .desc = "MWAIT 0x60",
+               .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 370,
+               .target_residency = 2500,
+               .enter = &intel_idle,
+               .enter_s2idle = intel_idle_s2idle, },
+       {
+               .enter = NULL }
+};
+
 static struct cpuidle_state gmt_cstates[] __initdata = {
        {
                .name = "C1",
@@ -1561,6 +1598,10 @@ static const struct idle_cpu idle_cpu_mtl_l __initconst = {
        .state_table = mtl_l_cstates,
 };
 
+static const struct idle_cpu idle_cpu_ptl __initconst = {
+       .state_table = ptl_cstates,
+};
+
 static const struct idle_cpu idle_cpu_gmt __initconst = {
        .state_table = gmt_cstates,
 };
@@ -1669,6 +1710,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
        X86_MATCH_VFM(INTEL_ALDERLAKE,          &idle_cpu_adl),
        X86_MATCH_VFM(INTEL_ALDERLAKE_L,        &idle_cpu_adl_l),
        X86_MATCH_VFM(INTEL_METEORLAKE_L,       &idle_cpu_mtl_l),
+       X86_MATCH_VFM(INTEL_PANTHERLAKE_L,      &idle_cpu_ptl),
        X86_MATCH_VFM(INTEL_ATOM_GRACEMONT,     &idle_cpu_gmt),
        X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X,   &idle_cpu_spr),
        X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X,    &idle_cpu_spr),