]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915/irq: abstract i9xx_display_irq_enable_mask()
authorJani Nikula <jani.nikula@intel.com>
Tue, 23 Sep 2025 14:31:06 +0000 (17:31 +0300)
committerJani Nikula <jani.nikula@intel.com>
Wed, 24 Sep 2025 06:31:07 +0000 (09:31 +0300)
Figure out the enable mask for display things in display code. Reuse the
same function for both i915 and i965 code, the end result remains the
same.

This removes a pair of DISPLAY_VER() and HAS_HOTPLUG() checks from core
irq code.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/dd7cd63a4019ff24098d565b67ea827df6b9ed45.1758637773.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_display_irq.c
drivers/gpu/drm/i915/display/intel_display_irq.h
drivers/gpu/drm/i915/i915_irq.c

index c6f367e6159e2725572d77f1b2299deedae6c9d9..4d51900123ea9006b8e53286f491fdb87908ff61 100644 (file)
@@ -1900,6 +1900,22 @@ void i9xx_display_irq_reset(struct intel_display *display)
        i9xx_pipestat_irq_reset(display);
 }
 
+u32 i9xx_display_irq_enable_mask(struct intel_display *display)
+{
+       u32 enable_mask;
+
+       enable_mask = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+               I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+
+       if (DISPLAY_VER(display) >= 3)
+               enable_mask |= I915_ASLE_INTERRUPT;
+
+       if (HAS_HOTPLUG(display))
+               enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
+
+       return enable_mask;
+}
+
 void i915_display_irq_postinstall(struct intel_display *display)
 {
        /*
index cee120347064428221294feaf83b46eeb5be5ba7..e44d88e0d7e72e6e1309ab182ef47188d2c266e9 100644 (file)
@@ -61,6 +61,7 @@ void vlv_display_irq_reset(struct intel_display *display);
 void gen8_display_irq_reset(struct intel_display *display);
 void gen11_display_irq_reset(struct intel_display *display);
 
+u32 i9xx_display_irq_enable_mask(struct intel_display *display);
 void i915_display_irq_postinstall(struct intel_display *display);
 void i965_display_irq_postinstall(struct intel_display *display);
 void vlv_display_irq_postinstall(struct intel_display *display);
index 04de02fc08d9eeeebb629d0c53d35fc840ac73a2..f9fbb88b9e26ad6b825f1cee3c14a6fb7b808729 100644 (file)
@@ -895,17 +895,9 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
 
        gen2_error_init(uncore, GEN2_ERROR_REGS, ~i9xx_error_mask(dev_priv));
 
-       enable_mask =
-               I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-               I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+       enable_mask = i9xx_display_irq_enable_mask(display) |
                I915_MASTER_ERROR_INTERRUPT;
 
-       if (DISPLAY_VER(display) >= 3)
-               enable_mask |= I915_ASLE_INTERRUPT;
-
-       if (HAS_HOTPLUG(display))
-               enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
-
        dev_priv->gen2_imr_mask = ~enable_mask;
 
        enable_mask |= I915_USER_INTERRUPT;
@@ -1010,11 +1002,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
 
        gen2_error_init(uncore, GEN2_ERROR_REGS, ~i965_error_mask(dev_priv));
 
-       enable_mask =
-               I915_ASLE_INTERRUPT |
-               I915_DISPLAY_PORT_INTERRUPT |
-               I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-               I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+       enable_mask = i9xx_display_irq_enable_mask(display) |
                I915_MASTER_ERROR_INTERRUPT;
 
        dev_priv->gen2_imr_mask = ~enable_mask;