]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE
authorKathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Tue, 12 Aug 2025 10:32:41 +0000 (16:02 +0530)
committerBjorn Andersson <andersson@kernel.org>
Tue, 12 Aug 2025 15:35:40 +0000 (10:35 -0500)
QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
first SE, which supports a 4-wire UART configuration suitable for
applications such as HS-UART.

Note that the required initialization for this SE is not handled by the
bootloader. Therefore, add the SE node in the device tree but keep it
reserved. Enable it once Linux gains support for configuring the SE,
allowing to use in relevant RDPs.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250812-ipq5424_hsuart-v4-1-f1faa7704ea9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
arch/arm64/boot/dts/qcom/ipq5424.dtsi

index 117f1785e8b8e3eef3ea4df005ac491ad4ed76b6..738618551203b9fb58ee3d6f7b7a46b38eea4bf4 100644 (file)
                };
        };
 
+       uart0_pins: uart0-default-state {
+               pins = "gpio10", "gpio11", "gpio12", "gpio13";
+               function = "uart0";
+               drive-strength = <8>;
+               bias-pull-down;
+       };
+
        pcie2_default_state: pcie2-default-state {
                pins = "gpio31";
                function = "gpio";
        };
 };
 
+&uart0 {
+       pinctrl-0 = <&uart0_pins>;
+       pinctrl-names = "default";
+       /*
+        * The required initialization for this SE is not handled by the
+        * bootloader. Therefore, keep the device in "reserved" state until
+        * linux gains support for configuring the SE.
+        */
+       status = "reserved";
+};
+
 &uart1 {
        pinctrl-0 = <&uart1_pins>;
        pinctrl-names = "default";
index 2eea8a078595103ca2d3912f41e3594820b52771..bd891e39f33e18864a1d4c2bd8399b8b7486fec5 100644 (file)
                        #address-cells = <2>;
                        #size-cells = <2>;
 
+                       uart0: serial@1a80000 {
+                               compatible = "qcom,geni-uart";
+                               reg = <0 0x01a80000 0 0x4000>;
+                               clocks = <&gcc GCC_QUPV3_UART0_CLK>;
+                               clock-names = "se";
+                               interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+                               status = "disabled";
+                       };
+
                        uart1: serial@1a84000 {
                                compatible = "qcom,geni-debug-uart";
                                reg = <0 0x01a84000 0 0x4000>;