]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
target/i386: clear CPU_INTERRUPT_SIPI for all accelerators
authorPaolo Bonzini <pbonzini@redhat.com>
Fri, 24 Oct 2025 07:18:43 +0000 (09:18 +0200)
committerPaolo Bonzini <pbonzini@redhat.com>
Tue, 28 Oct 2025 13:50:40 +0000 (14:50 +0100)
Similar to what commit df32e5c5 did for TCG; fixes boot with multiple
processors on WHPX and probably more accelerators

Fixes: df32e5c568c ("i386/cpu: Prevent delivering SIPI during SMM in TCG mode", 2025-10-14)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3178
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/i386/hvf/x86hvf.c
target/i386/kvm/kvm.c
target/i386/nvmm/nvmm-all.c
target/i386/whpx/whpx-all.c

index a502437c3031ee8a172f721b079fbe7108c69c4b..3838c9f5a6fca65215a5acba7b093f0649e30047 100644 (file)
@@ -446,6 +446,7 @@ int hvf_process_events(CPUState *cs)
         cs->halted = 0;
     }
     if (cpu_test_interrupt(cs, CPU_INTERRUPT_SIPI)) {
+        cpu_reset_interrupt(cs, CPU_INTERRUPT_SIPI);
         cpu_synchronize_state(cs);
         do_cpu_sipi(cpu);
     }
index 4dea1ed8f0f3de3914783c5f8f6a214e77d57a6c..60c798113823dabea1c76f8655da229a9a41809d 100644 (file)
@@ -5659,6 +5659,7 @@ int kvm_arch_process_async_events(CPUState *cs)
         cs->halted = 0;
     }
     if (cpu_test_interrupt(cs, CPU_INTERRUPT_SIPI)) {
+        cpu_reset_interrupt(cs, CPU_INTERRUPT_SIPI);
         kvm_cpu_synchronize_state(cs);
         do_cpu_sipi(cpu);
     }
index 2e442baf4b7151d5fc490573b62f5dc3f8affd87..b9bd9ed985a72198c11878b465ed3e74ad1a9ecc 100644 (file)
@@ -709,6 +709,7 @@ nvmm_vcpu_loop(CPUState *cpu)
         cpu->halted = false;
     }
     if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SIPI)) {
+        cpu_reset_interrupt(cpu, CPU_INTERRUPT_SIPI);
         nvmm_cpu_synchronize_state(cpu);
         do_cpu_sipi(x86_cpu);
     }
index 256761834c9759079ad778f9b5069b314b6ba6f7..6bf8d5f4bbbc30039905e63f22255838673d629f 100644 (file)
@@ -1621,6 +1621,7 @@ static void whpx_vcpu_process_async_events(CPUState *cpu)
     }
 
     if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SIPI)) {
+        cpu_reset_interrupt(cpu, CPU_INTERRUPT_SIPI);
         whpx_cpu_synchronize_state(cpu);
         do_cpu_sipi(x86_cpu);
     }