cxl/region: check interleave capability

[ Upstream commit 84328c5acebc10c8cdcf17283ab6c6d548885bfc ]

Since interleave capability is not verified, if the interleave
capability of a target does not match the region need, committing decoder
should have failed at the device end.

In order to checkout this error as quickly as possible, driver needs
to check the interleave capability of target during attaching it to
region.

Per CXL specification r3.1(8.2.4.20.1 CXL HDM Decoder Capability Register),
bits 11 and 12 indicate the capability to establish interleaving in 3, 6,
12 and 16 ways. If these bits are not set, the target cannot be attached to
a region utilizing such interleave ways.

Additionally, bits 8 and 9 represent the capability of the bits used for
interleaving in the address, Linux tracks this in the cxl_port
interleave_mask.

Per CXL specification r3.1(8.2.4.20.13 Decoder Protection):
  eIW means encoded Interleave Ways.
  eIG means encoded Interleave Granularity.

  in HPA:
  if eIW is 0 or 8 (interleave ways: 1, 3), all the bits of HPA are used,
  the interleave bits are none, the following check is ignored.

  if eIW is less than 8 (interleave ways: 2, 4, 8, 16), the interleave bits
  start at bit position eIG + 8 and end at eIG + eIW + 8 - 1.

  if eIW is greater than 8 (interleave ways: 6, 12), the interleave bits
  start at bit position eIG + 8 and end at eIG + eIW - 1.

  if the interleave mask is insufficient to cover the required interleave
  bits, the target cannot be attached to the region.

Fixes: 384e624bb211 ("cxl/region: Attach endpoint decoders")
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/20240614084755.59503-2-yaoxt.fnst@fujitsu.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 7d97790b893d709b74fef1d66c05a6ca4150401f..e01c16fdc757511f34a530ffad8e659bf81e2037 100644 (file)
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -52,6 +52,14 @@ int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
        struct cxl_dport *dport = NULL;
        int single_port_map[1];
        unsigned long index;
+       struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
+
+       /*
+        * Capability checks are moot for passthrough decoders, support
+        * any and all possibilities.
+        */
+       cxlhdm->interleave_mask = ~0U;
+       cxlhdm->iw_cap_mask = ~0UL;
 
        cxlsd = cxl_switch_decoder_alloc(port, 1);
        if (IS_ERR(cxlsd))
@@ -79,6 +87,11 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
                cxlhdm->interleave_mask |= GENMASK(11, 8);
        if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap))
                cxlhdm->interleave_mask |= GENMASK(14, 12);
+       cxlhdm->iw_cap_mask = BIT(1) | BIT(2) | BIT(4) | BIT(8);
+       if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap))
+               cxlhdm->iw_cap_mask |= BIT(3) | BIT(6) | BIT(12);
+       if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap))
+               cxlhdm->iw_cap_mask |= BIT(16);
 }
 
 static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)

diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index a083893c0afe02a3ebdf4e0b1d8184fa06ef94ef..a600feb8a4ed51decb424d87296843a712c8c20a 100644 (file)
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -1101,6 +1101,26 @@ static int cxl_port_attach_region(struct cxl_port *port,
        }
        cxld = cxl_rr->decoder;
 
+       /*
+        * the number of targets should not exceed the target_count
+        * of the decoder
+        */
+       if (is_switch_decoder(&cxld->dev)) {
+               struct cxl_switch_decoder *cxlsd;
+
+               cxlsd = to_cxl_switch_decoder(&cxld->dev);
+               if (cxl_rr->nr_targets > cxlsd->nr_targets) {
+                       dev_dbg(&cxlr->dev,
+                               "%s:%s %s add: %s:%s @ %d overflows targets: %d\n",
+                               dev_name(port->uport_dev), dev_name(&port->dev),
+                               dev_name(&cxld->dev), dev_name(&cxlmd->dev),
+                               dev_name(&cxled->cxld.dev), pos,
+                               cxlsd->nr_targets);
+                       rc = -ENXIO;
+                       goto out_erase;
+               }
+       }
+
        rc = cxl_rr_ep_add(cxl_rr, cxled);
        if (rc) {
                dev_dbg(&cxlr->dev,
@@ -1210,6 +1230,50 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled,
        return 0;
 }
 
+static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig)
+{
+       struct cxl_port *port = to_cxl_port(cxld->dev.parent);
+       struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
+       unsigned int interleave_mask;
+       u8 eiw;
+       u16 eig;
+       int high_pos, low_pos;
+
+       if (!test_bit(iw, &cxlhdm->iw_cap_mask))
+               return -ENXIO;
+       /*
+        * Per CXL specification r3.1(8.2.4.20.13 Decoder Protection),
+        * if eiw < 8:
+        *   DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + 8 + eiw]
+        *   DPAOFFSET[eig + 7: 0]  = HPAOFFSET[eig + 7: 0]
+        *
+        *   when the eiw is 0, all the bits of HPAOFFSET[51: 0] are used, the
+        *   interleave bits are none.
+        *
+        * if eiw >= 8:
+        *   DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + eiw] / 3
+        *   DPAOFFSET[eig + 7: 0]  = HPAOFFSET[eig + 7: 0]
+        *
+        *   when the eiw is 8, all the bits of HPAOFFSET[51: 0] are used, the
+        *   interleave bits are none.
+        */
+       ways_to_eiw(iw, &eiw);
+       if (eiw == 0 || eiw == 8)
+               return 0;
+
+       granularity_to_eig(ig, &eig);
+       if (eiw > 8)
+               high_pos = eiw + eig - 1;
+       else
+               high_pos = eiw + eig + 7;
+       low_pos = eig + 8;
+       interleave_mask = GENMASK(high_pos, low_pos);
+       if (interleave_mask & ~cxlhdm->interleave_mask)
+               return -ENXIO;
+
+       return 0;
+}
+
 static int cxl_port_setup_targets(struct cxl_port *port,
                                  struct cxl_region *cxlr,
                                  struct cxl_endpoint_decoder *cxled)
@@ -1360,6 +1424,15 @@ static int cxl_port_setup_targets(struct cxl_port *port,
                        return -ENXIO;
                }
        } else {
+               rc = check_interleave_cap(cxld, iw, ig);
+               if (rc) {
+                       dev_dbg(&cxlr->dev,
+                               "%s:%s iw: %d ig: %d is not supported\n",
+                               dev_name(port->uport_dev),
+                               dev_name(&port->dev), iw, ig);
+                       return rc;
+               }
+
                cxld->interleave_ways = iw;
                cxld->interleave_granularity = ig;
                cxld->hpa_range = (struct range) {
@@ -1796,6 +1869,15 @@ static int cxl_region_attach(struct cxl_region *cxlr,
        struct cxl_dport *dport;
        int rc = -ENXIO;
 
+       rc = check_interleave_cap(&cxled->cxld, p->interleave_ways,
+                                 p->interleave_granularity);
+       if (rc) {
+               dev_dbg(&cxlr->dev, "%s iw: %d ig: %d is not supported\n",
+                       dev_name(&cxled->cxld.dev), p->interleave_ways,
+                       p->interleave_granularity);
+               return rc;
+       }
+
        if (cxled->mode != cxlr->mode) {
                dev_dbg(&cxlr->dev, "%s region mode: %d mismatch: %d\n",
                        dev_name(&cxled->cxld.dev), cxlr->mode, cxled->mode);

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 2b82dcaf70aa6dbc837842322c0b95034eef3f37..6f9270f2faf96351497042fbf49756d3f5f6236b 100644 (file)
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -45,6 +45,8 @@
 #define   CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
 #define   CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
 #define   CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
+#define   CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11)
+#define   CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12)
 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4
 #define   CXL_HDM_DECODER_ENABLE BIT(1)
 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)

diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 36cee9c30cebd20488ec5afd216187ef82497e54..07e65a7605f3eae0beacd2ba55de3d61c394ead7 100644 (file)
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -848,11 +848,21 @@ static inline void cxl_mem_active_dec(void)
 
 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
 
+/**
+ * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities
+ * @regs: mapped registers, see devm_cxl_setup_hdm()
+ * @decoder_count: number of decoders for this port
+ * @target_count: for switch decoders, max downstream port targets
+ * @interleave_mask: interleave granularity capability, see check_interleave_cap()
+ * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap()
+ * @port: mapped cxl_port, see devm_cxl_setup_hdm()
+ */
 struct cxl_hdm {
        struct cxl_component_regs regs;
        unsigned int decoder_count;
        unsigned int target_count;
        unsigned int interleave_mask;
+       unsigned long iw_cap_mask;
        struct cxl_port *port;
 };
 

diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index 3482248aa34424e1d690ecea1faef822d152edd3..90d5afd52dd06b7ce904562c6ebe0813ff273c6b 100644 (file)
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -630,11 +630,15 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port,
                                          struct cxl_endpoint_dvsec_info *info)
 {
        struct cxl_hdm *cxlhdm = devm_kzalloc(&port->dev, sizeof(*cxlhdm), GFP_KERNEL);
+       struct device *dev = &port->dev;
 
        if (!cxlhdm)
                return ERR_PTR(-ENOMEM);
 
        cxlhdm->port = port;
+       cxlhdm->interleave_mask = ~0U;
+       cxlhdm->iw_cap_mask = ~0UL;
+       dev_set_drvdata(dev, cxlhdm);
        return cxlhdm;
 }