return 0;
}
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 ear)
+{
+ u8 cmd;
+ int ret;
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ return ret;
+ }
+
+ cmd = CMD_BANKADDR_BRWR;
+ ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &ear, 1);
+ if (ret) {
+ debug("SF: fail to write bank addr register\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret < 0) {
+ debug("SF: write config register timed out\n");
+ return ret;
+ }
+
+ return 0;
+}
+
/*
* The following table holds all device probe functions
*
#define CMD_ERASE_64K 0xd8
#define CMD_ERASE_CHIP 0xc7
+/* Bank addr acess commands */
+#define CMD_BANKADDR_BRWR 0x17
+
/* Common status */
#define STATUS_WIP 0x01
/* Program the status register. */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+/* Program the bank address register */
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 ear);
+
/*
* Same as spi_flash_cmd_read() except it also claims/releases the SPI
* bus. Used as common part of the ->read() operation.