drm/amd/display: Setup Second Stutter Watermark Implementation

[WHY & HOW]
Setup initial changes required to program another set of watermarks
for a 2nd stutter mode. The 2nd stutter mode will be lower power but
have higher enter/exit latencies.

PMFW to choose which stutter mode to use based on stutter efficiences
to see if original stutter (LP1) or low power stutter (LP2) will result
in better power savings.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 1ab05eabbddbd3f76d76f6aa702b3d6572455935..29aaa38cc784a3f69387814a2beec0b4b7a6a73e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -694,6 +694,15 @@ struct dc_clocks {
        int idle_fclk_khz;
        int subvp_prefetch_dramclk_khz;
        int subvp_prefetch_fclk_khz;
+
+       /* Stutter efficiency is technically not clock values
+        * but stored here so the values are part of the update_clocks call similar to num_ways
+        * Efficiencies are stored as percentage (0-100)
+        */
+       struct {
+               uint8_t base_efficiency; //LP1
+               uint8_t low_power_efficiency; //LP2
+       } stutter_efficiency;
 };
 
 struct dc_bw_validation_profile {

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
index a06217a9eef60a2ea14151ca4a68c13e073bfb9b..23fdb17f851a3000939d35843e2dbe17ece73055 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
@@ -1165,6 +1165,8 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state
        context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz;
        context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz;
        context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;
+       context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;
+       context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;
 }
 
 static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h
index b05030926ce854575f902c2442b3a49087de716c..91955bbe24b868731f5ad356d36c5822a4d9699a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h
@@ -159,6 +159,8 @@ struct dml2_dchub_watermark_regs {
        uint32_t sr_exit;
        uint32_t sr_enter_z8;
        uint32_t sr_exit_z8;
+       uint32_t sr_enter_low_power;
+       uint32_t sr_exit_low_power;
        uint32_t uclk_pstate;
        uint32_t fclk_pstate;
        uint32_t temp_read_or_ppt;

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h
index 8c9f414aa6bf9c3e456ae6708ca93f55d2345ad5..176f559476644e12fbdb3dae8833fb5f0fb363f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h
@@ -96,6 +96,8 @@ struct dml2_soc_power_management_parameters {
        double g7_temperature_read_blackout_us;
        double stutter_enter_plus_exit_latency_us;
        double stutter_exit_latency_us;
+       double low_power_stutter_enter_plus_exit_latency_us;
+       double low_power_stutter_exit_latency_us;
        double z8_stutter_enter_plus_exit_latency_us;
        double z8_stutter_exit_latency_us;
        double z8_min_idle_time;

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
index 98c0234e2f474e004d3eeaa739f21613ee0d98d8..7de10a95cfdb1d3a868748745cc384cc771f91c7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
@@ -417,6 +417,8 @@ struct dml2_display_cfg_programming {
 
        struct {
                bool supported_in_blank; // Changing to configurations where this is false requires stutter to be disabled during the transition
+               uint8_t base_percent_efficiency; //LP1
+               uint8_t low_power_percent_efficiency; //LP2
        } stutter;
 
        struct {

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
index 28687565ac222ff0c9d670ac806afcfeb0c396d9..ffb8c09f37a5ce4d0adc6e3f3d517dad6fd93daa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
@@ -201,6 +201,8 @@ struct dml2_core_internal_watermarks {
        double WritebackFCLKChangeWatermark;
        double StutterExitWatermark;
        double StutterEnterPlusExitWatermark;
+       double LowPowerStutterExitWatermark;
+       double LowPowerStutterEnterPlusExitWatermark;
        double Z8StutterExitWatermark;
        double Z8StutterEnterPlusExitWatermark;
        double USRRetrainingWatermark;
@@ -877,6 +879,9 @@ struct dml2_core_internal_mode_program {
        double Z8StutterEfficiency;
        unsigned int Z8NumberOfStutterBurstsPerFrame;
        double Z8StutterEfficiencyNotIncludingVBlank;
+       double LowPowerStutterEfficiency;
+       double LowPowerStutterEfficiencyNotIncludingVBlank;
+       unsigned int LowPowerNumberOfStutterBurstsPerFrame;
        double StutterPeriod;
        double Z8StutterEfficiencyBestCase;
        unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
@@ -1016,6 +1021,8 @@ struct dml2_core_internal_SOCParametersList {
        double FCLKChangeLatency;
        double SRExitTime;
        double SREnterPlusExitTime;
+       double SRExitTimeLowPower;
+       double SREnterPlusExitTimeLowPower;
        double SRExitZ8Time;
        double SREnterPlusExitZ8Time;
        double USRRetrainingLatency;
@@ -1851,9 +1858,11 @@ struct dml2_core_calcs_CalculateStutterEfficiency_params {
        unsigned int CompbufReservedSpaceZs;
        bool hw_debug5;
        double SRExitTime;
+       double SRExitTimeLowPower;
        double SRExitZ8Time;
        bool SynchronizeTimings;
        double StutterEnterPlusExitWatermark;
+       double LowPowerStutterEnterPlusExitWatermark;
        double Z8StutterEnterPlusExitWatermark;
        bool ProgressiveToInterlaceUnitInOPP;
        double *MinTTUVBlank;
@@ -1879,7 +1888,10 @@ struct dml2_core_calcs_CalculateStutterEfficiency_params {
        // output
        double *StutterEfficiencyNotIncludingVBlank;
        double *StutterEfficiency;
+       double *LowPowerStutterEfficiencyNotIncludingVBlank;
+       double *LowPowerStutterEfficiency;
        unsigned int *NumberOfStutterBurstsPerFrame;
+       unsigned int *LowPowerNumberOfStutterBurstsPerFrame;
        double *Z8StutterEfficiencyNotIncludingVBlank;
        double *Z8StutterEfficiency;
        unsigned int *Z8NumberOfStutterBurstsPerFrame;