dts: zynq_cse: Add dts files for all mini u-boot qspi configurations

This patch adds dts files for all qspi configurations of mini
u-boot. This lets user to compile the required qspi configuration
image by specifying the DEVICE_TREE=<dts filename> along with make.

This patch also renames zynq-cse-qspi dts to dtsi so that
it will be used in respective dts files. This also
needs to update defconfig and make files respectively.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1ab7e2cab7e694b9de085e1a510733fe93645c29..d68690e04fd3d3080c030a86507f94e4870f0214 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -101,7 +101,13 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
        zynq-microzed.dtb \
        zynq-cc108.dtb \
        zynq-cse-nand.dtb \
-       zynq-cse-qspi.dtb \
+       zynq-cse-qspi-parallel.dtb \
+       zynq-cse-qspi-single.dtb \
+       zynq-cse-qspi-stacked.dtb \
+       zynq-cse-qspi-x1-single.dtb \
+       zynq-cse-qspi-x1-stacked.dtb \
+       zynq-cse-qspi-x2-single.dtb \
+       zynq-cse-qspi-x2-stacked.dtb \
        zynq-picozed.dtb \
        zynq-topic-miami.dtb \
        zynq-topic-miamiplus.dtb \

diff --git a/arch/arm/dts/zynq-cse-qspi-parallel.dts b/arch/arm/dts/zynq-cse-qspi-parallel.dts
new file mode 100644 (file)
index 0000000..52e6ce7
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-parallel.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx CSE QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+       is-dual = <1>;
+       spi-rx-bus-width = <4>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-single.dts b/arch/arm/dts/zynq-cse-qspi-single.dts
new file mode 100644 (file)
index 0000000..bc08303
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-single.dts
@@ -0,0 +1,13 @@
+/*
+ * Xilinx CSE QSPI single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+       spi-rx-bus-width = <4>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-stacked.dts b/arch/arm/dts/zynq-cse-qspi-stacked.dts
new file mode 100644 (file)
index 0000000..e19bf3e
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-stacked.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx CSE QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+       is-dual = <0>;
+       spi-rx-bus-width = <4>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-x1-single.dts b/arch/arm/dts/zynq-cse-qspi-x1-single.dts
new file mode 100644 (file)
index 0000000..f660a52
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x1-single.dts
@@ -0,0 +1,13 @@
+/*
+ * Xilinx CSE QSPI x1 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+       spi-rx-bus-width = <1>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts
new file mode 100644 (file)
index 0000000..cf97fc4
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx CSE QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+       is-dual = <0>;
+       spi-rx-bus-width = <1>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-x2-single.dts b/arch/arm/dts/zynq-cse-qspi-x2-single.dts
new file mode 100644 (file)
index 0000000..1e54974
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x2-single.dts
@@ -0,0 +1,13 @@
+/*
+ * Xilinx CSE QSPI x2 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+       spi-rx-bus-width = <2>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts
new file mode 100644 (file)
index 0000000..796449f
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx CSE QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+       is-dual = <0>;
+       spi-rx-bus-width = <2>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi.dts b/arch/arm/dts/zynq-cse-qspi.dtsi
similarity index 100%
rename from arch/arm/dts/zynq-cse-qspi.dts
rename to arch/arm/dts/zynq-cse-qspi.dtsi

diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 1f5b6f5a98a1f5edb50cc8633f671cee2e6255e4..223f960838d1fb6d4b813f7c2bbc784b9be3816f 100644 (file)
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_cse"
 CONFIG_ARCH_ZYNQ=y
 # CONFIG_MMC is not set
 CONFIG_SYS_TEXT_BASE=0xFFFC0000
-CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi"
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
 CONFIG_BOOTDELAY=-1
 CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_CPUINFO is not set