arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC

As per S905 and S905X datasheet add missing cache information to
the Amlogic GXBB and GXL SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-2-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 7d99ca44e660c2763f85fca98c75864b4f8e8969..c1d8e81d95cb9b7758d8d12c230be13d4311e5e4 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -95,6 +95,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
                        #cooling-cells = <2>;
@@ -105,6 +111,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
                        #cooling-cells = <2>;
@@ -115,6 +127,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
                        #cooling-cells = <2>;
@@ -125,6 +143,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
                        #cooling-cells = <2>;
@@ -134,6 +158,9 @@
                        compatible = "cache";
                        cache-level = <2>;
                        cache-unified;
+                       cache-size = <0x80000>; /* L2. 512 KB */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };