drm/rcar-du: dsi: Fix 1/2/3 lane support

Remove fixed PPI lane count setup. The R-Car DSI host is capable
of operating in 1..4 DSI lane mode. Remove the hard-coded 4-lane
configuration from PPI register settings and instead configure
the PPI lane count according to lane count information already
obtained by this driver instance.

Configure TXSETR register to match PPI lane count. The R-Car V4H
Reference Manual R19UH0186EJ0121 Rev.1.21 section 67.2.2.3 Tx Set
Register (TXSETR), field LANECNT description indicates that the
TXSETR register LANECNT bitfield lane count must be configured
such, that it matches lane count configuration in PPISETR register
DLEN bitfield. Make sure the LANECNT and DLEN bitfields are
configured to match.

Fixes: 155358310f01 ("drm: rcar-du: Add R-Car DSI driver")
Cc: stable@vger.kernel.org
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20250813210840.97621-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
index 1af4c73f7a887712aef8c8176b0d0338d9ca9727..952c3efb74da9b58aba55fb8f71325399631ce99 100644 (file)
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
@@ -576,7 +576,10 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi,
        udelay(10);
        rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
 
-       ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN;
+       rcar_mipi_dsi_clr(dsi, TXSETR, TXSETR_LANECNT_MASK);
+       rcar_mipi_dsi_set(dsi, TXSETR, dsi->lanes - 1);
+
+       ppisetr = ((BIT(dsi->lanes) - 1) & PPISETR_DLEN_MASK) | PPISETR_CLEN;
        rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
 
        rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);

diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
index a6b276f1d6ee15901e133080fe5bbb5e0376283d..a54c7eb4113b93c9991ed078b49ecd66552e66b7 100644 (file)
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
@@ -12,6 +12,9 @@
 #define LINKSR_LPBUSY                  (1 << 1)
 #define LINKSR_HSBUSY                  (1 << 0)
 
+#define TXSETR                         0x100
+#define TXSETR_LANECNT_MASK            (0x3 << 0)
+
 /*
  * Video Mode Register
  */
@@ -80,10 +83,7 @@
  * PHY-Protocol Interface (PPI) Registers
  */
 #define PPISETR                                0x700
-#define PPISETR_DLEN_0                 (0x1 << 0)
-#define PPISETR_DLEN_1                 (0x3 << 0)
-#define PPISETR_DLEN_2                 (0x7 << 0)
-#define PPISETR_DLEN_3                 (0xf << 0)
+#define PPISETR_DLEN_MASK              (0xf << 0)
 #define PPISETR_CLEN                   (1 << 8)
 
 #define PPICLCR                                0x710