arm64: dts: qcom: sm8650: Fix domain-idle-state for CPU2

[ Upstream commit 9bb5ca464100e7c8f2d740148088f60e04fed8ed ]

On SM8650 the CPUs 0-1 are "silver" (Cortex-A520), CPU 2-6 are "gold"
(Cortex-A720) and CPU 7 is "gold-plus" (Cortex-X4).

So reference the correct "gold" idle-state for CPU core 2.

Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250314-sm8650-cpu2-sleep-v1-1-31d5c7c87a5d@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 3a7daeb2c12e35eff4965307ef1d6dbf35f7e420..72e3dcd495c3b5a43fee567f2a340c5c1a1c16d9 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -426,7 +426,7 @@
                cpu_pd2: power-domain-cpu2 {
                        #power-domain-cells = <0>;
                        power-domains = <&cluster_pd>;
-                       domain-idle-states = <&silver_cpu_sleep_0>;
+                       domain-idle-states = <&gold_cpu_sleep_0>;
                };
 
                cpu_pd3: power-domain-cpu3 {