#include "cpu_bits.h"
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
+#include "system/memory.h"
#ifdef TARGET_RISCV64
#define PTE_HEADER_FIELDS "vaddr paddr "\
attr & PTE_D ? 'd' : '-');
}
-static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
+static void walk_pte(Monitor *mon, AddressSpace *as,
+ hwaddr base, target_ulong start,
int level, int ptidxbits, int ptesize, int va_bits,
target_ulong *vbase, hwaddr *pbase, hwaddr *last_paddr,
target_ulong *last_size, int *last_attr)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
hwaddr pte_addr;
hwaddr paddr;
target_ulong last_start = -1;
for (idx = 0; idx < (1UL << ptidxbits); idx++) {
pte_addr = base + idx * ptesize;
- cpu_physical_memory_read(pte_addr, &pte, ptesize);
+ address_space_read(as, pte_addr, attrs, &pte, ptesize);
paddr = (hwaddr)(pte >> PTE_PPN_SHIFT) << PGSHIFT;
attr = pte & 0xff;
*last_size = pgsize;
} else {
/* pointer to the next level of the page table */
- walk_pte(mon, paddr, start, level - 1, ptidxbits, ptesize,
+ walk_pte(mon, as, paddr, start, level - 1, ptidxbits, ptesize,
va_bits, vbase, pbase, last_paddr,
last_size, last_attr);
}
static void mem_info_svxx(Monitor *mon, CPUArchState *env)
{
+ AddressSpace *as = env_cpu(env)->as;
int levels, ptidxbits, ptesize, vm, va_bits;
hwaddr base;
target_ulong vbase;
last_attr = 0;
/* walk page tables, starting from address 0 */
- walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits,
+ walk_pte(mon, as, base, 0, levels - 1, ptidxbits, ptesize, va_bits,
&vbase, &pbase, &last_paddr, &last_size, &last_attr);
/* don't forget the last one */