dt-bindings: Remove outdated cpufreq-dt.txt

The information present in this file is outdated and doesn't serve any
purpose with the current design of the driver.

Remove the outdated file.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
[ Viresh: Rewrite commit log ]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt
deleted file mode 100644 (file)
index 1d7e491..0000000
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-Generic cpufreq driver
-
-It is a generic DT based cpufreq driver for frequency management.  It supports
-both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share
-clock and voltage across all CPUs.
-
-Both required and optional properties listed below must be defined
-under node /cpus/cpu@0.
-
-Required properties:
-- None
-
-Optional properties:
-- operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for
-  details. OPPs *must* be supplied either via DT, i.e. this property, or
-  populated at runtime.
-- clock-latency: Specify the possible maximum transition latency for clock,
-  in unit of nanoseconds.
-- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
-- #cooling-cells:
-     Please refer to
-     Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
-
-Examples:
-
-cpus {
-       #address-cells = <1>;
-       #size-cells = <0>;
-
-       cpu@0 {
-               compatible = "arm,cortex-a9";
-               reg = <0>;
-               next-level-cache = <&L2>;
-               operating-points = <
-                       /* kHz    uV */
-                       792000  1100000
-                       396000  950000
-                       198000  850000
-               >;
-               clock-latency = <61036>; /* two CLK32 periods */
-               #cooling-cells = <2>;
-       };
-
-       cpu@1 {
-               compatible = "arm,cortex-a9";
-               reg = <1>;
-               next-level-cache = <&L2>;
-       };
-
-       cpu@2 {
-               compatible = "arm,cortex-a9";
-               reg = <2>;
-               next-level-cache = <&L2>;
-       };
-
-       cpu@3 {
-               compatible = "arm,cortex-a9";
-               reg = <3>;
-               next-level-cache = <&L2>;
-       };
-};