arm64/mm: Directly use TTBRx_EL1_ASID_MASK

Replace all TTBR_ASID_MASK macro instances with TTBRx_EL1_ASID_MASK which
is a standard field mask from tools sysreg format. Drop the now redundant
custom macro TTBR_ASID_MASK. No functional change.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oupton@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: kvmarm@lists.linux.dev
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h
index 9148f5a3196815aadf8a267c5681c1addf2c54aa..12aa6a28324966378470226b6dc7a9e3ab5a9337 100644 (file)
--- a/arch/arm64/include/asm/asm-uaccess.h
+++ b/arch/arm64/include/asm/asm-uaccess.h
@@ -15,7 +15,7 @@
 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
        .macro  __uaccess_ttbr0_disable, tmp1
        mrs     \tmp1, ttbr1_el1                        // swapper_pg_dir
-       bic     \tmp1, \tmp1, #TTBR_ASID_MASK
+       bic     \tmp1, \tmp1, #TTBRx_EL1_ASID_MASK
        sub     \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET  // reserved_pg_dir
        msr     ttbr0_el1, \tmp1                        // set reserved TTBR0_EL1
        add     \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET

diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index 137a173df1ff88b46734ea9c4503c23ee60b4929..019b36cda380089cba370de39e7027a36e952199 100644 (file)
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -10,7 +10,6 @@
 #define MMCF_AARCH32   0x1     /* mm context flag for AArch32 executables */
 #define USER_ASID_BIT  48
 #define USER_ASID_FLAG (UL(1) << USER_ASID_BIT)
-#define TTBR_ASID_MASK (UL(0xffff) << 48)
 
 #ifndef __ASSEMBLER__
 

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index cc80af59c69ecfe6629d1e4a9dad08463cc7023f..803b687581527572d4b6762b563c7b4580401f6a 100644 (file)
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -210,7 +210,8 @@ static inline void update_saved_ttbr0(struct task_struct *tsk,
        if (mm == &init_mm)
                ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
        else
-               ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48;
+               ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) |
+                      FIELD_PREP(TTBRx_EL1_ASID_MASK, ASID(mm));
 
        WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr);
 }

diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 9810106a3f664a2df29851410e41079686f052c2..86dfc356ee6e891aaa6468db434de400c6587469 100644 (file)
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -62,7 +62,7 @@ static inline void __uaccess_ttbr0_disable(void)
 
        local_irq_save(flags);
        ttbr = read_sysreg(ttbr1_el1);
-       ttbr &= ~TTBR_ASID_MASK;
+       ttbr &= ~TTBRx_EL1_ASID_MASK;
        /* reserved_pg_dir placed before swapper_pg_dir */
        write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1);
        /* Set reserved ASID */
@@ -85,8 +85,8 @@ static inline void __uaccess_ttbr0_enable(void)
 
        /* Restore active ASID */
        ttbr1 = read_sysreg(ttbr1_el1);
-       ttbr1 &= ~TTBR_ASID_MASK;               /* safety measure */
-       ttbr1 |= ttbr0 & TTBR_ASID_MASK;
+       ttbr1 &= ~TTBRx_EL1_ASID_MASK;          /* safety measure */
+       ttbr1 |= ttbr0 & TTBRx_EL1_ASID_MASK;
        write_sysreg(ttbr1, ttbr1_el1);
 
        /* Restore user page table */

diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index f8018b5c1f9ad07eae82627decbe67c5524e5cb7..9e1bcc821a16e8a40c213d79061f284ae6497157 100644 (file)
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -473,7 +473,7 @@ alternative_else_nop_endif
         */
 SYM_CODE_START_LOCAL(__swpan_entry_el1)
        mrs     x21, ttbr0_el1
-       tst     x21, #TTBR_ASID_MASK            // Check for the reserved ASID
+       tst     x21, #TTBRx_EL1_ASID_MASK       // Check for the reserved ASID
        orr     x23, x23, #PSR_PAN_BIT          // Set the emulated PAN in the saved SPSR
        b.eq    1f                              // TTBR0 access already disabled
        and     x23, x23, #~PSR_PAN_BIT         // Clear the emulated PAN in the saved SPSR

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index b2ac062463273f44e8983e37e253270e2dbba803..718c495832d0a582747e3f230dcf0d1b25c5d29f 100644 (file)
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -358,11 +358,11 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm)
 
        /* SW PAN needs a copy of the ASID in TTBR0 for entry */
        if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN))
-               ttbr0 |= FIELD_PREP(TTBR_ASID_MASK, asid);
+               ttbr0 |= FIELD_PREP(TTBRx_EL1_ASID_MASK, asid);
 
        /* Set ASID in TTBR1 since TCR.A1 is set */
-       ttbr1 &= ~TTBR_ASID_MASK;
-       ttbr1 |= FIELD_PREP(TTBR_ASID_MASK, asid);
+       ttbr1 &= ~TTBRx_EL1_ASID_MASK;
+       ttbr1 |= FIELD_PREP(TTBRx_EL1_ASID_MASK, asid);
 
        cpu_set_reserved_ttbr0_nosync();
        write_sysreg(ttbr1, ttbr1_el1);