drm/msm: Fix snapshotting a7xx indexed regs

We were overwriting the last indexed reg (CP_ROQ) and we were
snapshotting the same CP_MEMPOOL block twice instead of snapshotting
CP_BV_MEMPOOL as intended.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/575920/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 91a564a24dbecd3a29e223c2f71e0dcfb8b6e156..54bf9e2fbcc9fe88feb28b7f3bcd1f17a49f9d8f 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -1068,8 +1068,8 @@ static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
 
        /* Get the contents of the CP_BV mempool */
        for (i = 0; i < mempool_count; i++)
-               a6xx_get_indexed_regs(gpu, a6xx_state, a7xx_cp_bv_mempool_indexed,
-                       &a6xx_state->indexed_regs[indexed_count - 1 + i]);
+               a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_cp_bv_mempool_indexed[i],
+                       &a6xx_state->indexed_regs[indexed_count + i]);
 
        gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0);
        gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0);