powerpc/8xx: Remove left-over instruction and comments in DataStoreTLBMiss handler

Commit ac9f97ff8b32 ("powerpc/8xx: Inconditionally use task PGDIR in
DTLB misses") removed the test that needed the valeur in SPRN_EPN but
failed to remove the read.

Remove it.

And remove related comments, including the very same comment
in InstructionTLBMiss that should have been removed by
commit 33c527522f39 ("powerpc/8xx: Inconditionally use task PGDIR in
ITLB misses").

Also update the comment about absence of a second level table which
has been handled implicitely since commit 5ddb75cee5af ("powerpc/8xx:
remove tests on PGDIR entry validity").

Fixes: ac9f97ff8b32 ("powerpc/8xx: Inconditionally use task PGDIR in DTLB misses")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/5811c8d1d6187f280ad140d6c0ad6010e41eeaeb.1755361995.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 78942fd6b4b97ccb9e547eb2d8e9e3ab24f5ab57..393e19ee13222d9b5c9197f8cd0ac2f6fe6549ed 100644 (file)
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -162,7 +162,7 @@ instruction_counter:
  * For the MPC8xx, this is a software tablewalk to load the instruction
  * TLB.  The task switch loads the M_TWB register with the pointer to the first
  * level table.
- * If we discover there is no second level table (value is zero) or if there
+ * If there is no second level table (value is zero) or if there
  * is an invalid pte, we load that into the TLB, which causes another fault
  * into the TLB Error interrupt where we can handle such problems.
  * We have to use the MD_xxx registers for the tablewalk because the
@@ -183,9 +183,6 @@ instruction_counter:
        mtspr   SPRN_SPRG_SCRATCH2, r10
        mtspr   SPRN_M_TW, r11
 
-       /* If we are faulting a kernel address, we have to use the
-        * kernel page tables.
-        */
        mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
        INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)
        mtspr   SPRN_MD_EPN, r10
@@ -228,10 +225,6 @@ instruction_counter:
        mtspr   SPRN_SPRG_SCRATCH2, r10
        mtspr   SPRN_M_TW, r11
 
-       /* If we are faulting a kernel address, we have to use the
-        * kernel page tables.
-        */
-       mfspr   r10, SPRN_MD_EPN
        mfspr   r10, SPRN_M_TWB /* Get level 1 table */
        lwz     r11, 0(r10)     /* Get level 1 entry */