qualcommbe: ipq9574: enable uniphy 25MHz clock output

Some board designs feed an external PHY its reference clock from the
uniphy 25MHz clock output instead of a local crystal. Enable the
output when the devicetree opts in with "qcom,uniphy-clkout-25mhz".

The clock output register only becomes writable once the PLL reset
and calibration have completed, so program it at the end of the mode
configuration rather than at probe time.

Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/24033
Signed-off-by: Robert Marko <robimarko@gmail.com>

diff --git a/target/linux/qualcommbe/patches-6.18/0358-net-pcs-qcom-ipq9574-enable-uniphy-25MHz-clock-output.patch b/target/linux/qualcommbe/patches-6.18/0358-net-pcs-qcom-ipq9574-enable-uniphy-25MHz-clock-output.patch
new file mode 100644 (file)
index 0000000..101dcc3
--- /dev/null
+++ b/target/linux/qualcommbe/patches-6.18/0358-net-pcs-qcom-ipq9574-enable-uniphy-25MHz-clock-output.patch
@@ -0,0 +1,50 @@
+From: Kenneth Kasilag <kenneth@kasilag.me>
+Date: Wed, 01 Jul 2026 00:00:00 +0000
+Subject: [PATCH] net: pcs: qcom-ipq9574: enable uniphy 25MHz clock output
+
+Some board designs feed an external PHY its reference clock from the
+uniphy 25MHz clock output instead of a local crystal. Enable the
+output when the devicetree opts in with "qcom,uniphy-clkout-25mhz".
+
+The clock output register only becomes writable once the PLL reset
+and calibration have completed, so program it at the end of the mode
+configuration rather than at probe time.
+
+Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
+---
+ drivers/net/pcs/pcs-qcom-ipq9574.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
+@@ -23,6 +23,11 @@
+ #define PCS_CALIBRATION                       0x1e0
+ #define PCS_CALIBRATION_DONE          BIT(7)
+ 
++/* 25MHz reference clock output to an external PHY */
++#define PCS_CLKOUT_50M_CTRL           0x610
++#define PCS_CLKOUT_50M_25M_EN         BIT(0)
++#define PCS_CLKOUT_50M_DIV2_SEL               BIT(5)
++
+ #define PCS_MISC2                     0x218
+ #define PCS_MISC2_MODE_MASK           GENMASK(6, 5)
+ #define PCS_MISC2_MODE_SGMII          FIELD_PREP(PCS_MISC2_MODE_MASK, 0x1)
+@@ -377,6 +382,18 @@ static int ipq_pcs_config_mode(struct ip
+ 
+       qpcs->interface = interface;
+ 
++      /* The clock output register is only writable after PLL reset
++       * and calibration, so this cannot be done at probe.
++       */
++      if (of_property_read_bool(qpcs->dev->of_node,
++                                "qcom,uniphy-clkout-25mhz")) {
++              ret = regmap_set_bits(qpcs->regmap, PCS_CLKOUT_50M_CTRL,
++                                    PCS_CLKOUT_50M_25M_EN |
++                                    PCS_CLKOUT_50M_DIV2_SEL);
++              if (ret)
++                      return ret;
++      }
++
+       /* Configure the RX and TX clock to NSSCC as 125M or 312.5M based
+        * on current interface mode.
+        */