zynqmp: Get arm global timers running on RTL4.0

There is additional setup which needs to be done
on ep108 to get timers working.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 02c9b672b1cd45d879a310cfc235a2511b1c9d0e..55309d8811f234a2a89f9e65214ce026594b684c 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -24,15 +24,30 @@
 #define ZYNQ_SDHCI_BASEADDR1   0xFF170000
 
 #define ZYNQMP_CRL_APB_BASEADDR        0xFF5E0000
+#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT       0x1000000
 
 struct crlapb_regs {
-       u32 reserved0[128];
-       u32 boot_mode;
+       u32 reserved0[74];
+       u32 timestamp_ref_ctrl; /* 0x128 */
+       u32 reserved0_1[53];
+       u32 boot_mode; /* 0x200 */
        u32 reserved1[26];
 };
 
 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
 
+#define ZYNQMP_IOU_SCNTR       0xFF250000
+#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN   0x2
+#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x1
+
+struct iou_scntr {
+       u32 counter_control_register;
+       u32 reserved0[7];
+       u32 base_frequency_id_register;
+};
+
+#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
+
 /* Bootmode setting values */
 #define BOOT_MODES_MASK        0x0000000F
 #define QSPI_MODE      0x00000001

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 846a40359100bdc60c9b2602587a85998168f475..afe6737e4c75c539de25dec30aeefd52c251e0fe 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -18,6 +18,23 @@ int board_init(void)
        return 0;
 }
 
+int board_early_init_r(void)
+{
+       u32 val;
+
+       val = readl(&crlapb_base->timestamp_ref_ctrl);
+       val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+       writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+       /* Program freq register in System counter and enable system counter */
+       writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
+       writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
+              ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+              &iou_scntr->counter_control_register);
+
+       return 0;
+}
+
 int dram_init(void)
 {
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 2c69bcb1477763fda47a70f2eae3e7462e537cea..8d964f6d4f4ebee44e7a6818b33992815ab6a2d8 100644 (file)
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -180,6 +180,7 @@
 #define CONFIG_CMD_BOOTI
 #define CONFIG_CMD_UNZIP
 
+#define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_CLOCKS
 
 #endif /* __XILINX_ZYNQMP_H */