arm64: zynqmp: Do not call SMC from SPL

SPL is running before ATF in EL3 that's why SMCs can't be called because
there is nothing to call. zynqmp_mmio*() are doing direct read/write
accesses and this patch does the same.
PMUFW is up and running at this time and there is a way to talk to pmufw
via IPI but there is no reason to implement IPI stuff in SPL if we need
just simple read for getting clock driver to work.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 54afa9e034d61b6e1777e0d9297fd2037b90452d..d6941050541855fc4c505e91c3b99d55390e050d 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -109,6 +109,7 @@ unsigned int zynqmp_get_silicon_version(void)
 #define ZYNQMP_MMIO_READ       0xC2000014
 #define ZYNQMP_MMIO_WRITE      0xC2000013
 
+#ifndef CONFIG_SPL_BUILD
 static int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
                        u32 *ret_payload)
 {
@@ -155,3 +156,18 @@ int zynqmp_mmio_read(const u32 address, u32 *value)
 
        return ret;
 }
+#else
+int zynqmp_mmio_write(const u32 address,
+                     const u32 mask,
+                     const u32 value)
+{
+       panic_str("MMIO write not implemented\n");
+       return 0;
+}
+
+int zynqmp_mmio_read(const u32 address, u32 *value)
+{
+       *value = readl((ulong)address);
+       return 0;
+}
+#endif