arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL board

[ Upstream commit 162aadaa0df8217b0cc49d919dd00022fef65e78 ]

These signals are actively driven by the SoC or by the onboard
transceiver. There's no need to enable the internal pull resistors
and due to silicon errata ERR050080 let's disable the internal ones
to prevent any unwanted behavior in case they wear out.

Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
index 362f9360b4a51648c00870cab2f60c288f1a734e..67e768032320a94fc2b2434ef0190948bab11df3 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
@@ -288,19 +288,19 @@
 
        pinctrl_uart1: uart1grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX              0x140
-                       MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX             0x140
-                       MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B          0x140
-                       MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B          0x140
+                       MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX              0x0
+                       MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX             0x0
+                       MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B          0x0
+                       MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B          0x0
                >;
        };
 
        pinctrl_uart2: uart2grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX             0x140
-                       MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX              0x140
-                       MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B           0x140
-                       MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B           0x140
+                       MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX             0x0
+                       MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX              0x0
+                       MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B           0x0
+                       MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B           0x0
                >;
        };