config USB_MODE
bool "USB"
+config SW_USBHOST_MODE
+ bool "SW USBHOST_MODE"
+
+config SW_SATA_MODE
+ bool "SW SATA_MODE"
+
endchoice
++# Temporary Kconfig options which needs to be fixed
++config MINI_EMMC
++ bool
++
++config MINI_QSPI
++ bool
++
++config MINI_NAND
++ bool
++
++config SPI_GENERIC
++ bool
++
endif
config SYS_MALLOC_F_LEN
default 0x600
+config BOOT_INIT_FILE
+ string "boot.bin init register filename"
+ default ""
+ help
+ Add register writes to boot.bin format (max 256 pairs).
+ Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
+
++# Temporary Kconfig options which needs to be fixed
++config ZYNQ_M29EW_WB_HACK
++ bool
++
++config SYS_I2C_MUX_ADDR
++ int
++
++config SYS_I2C_MUX_EEPROM_SEL
++ int
++
endif
--- /dev/null
+ menu "SPL / TPL"
+
+ config SUPPORT_SPL
+ bool
+
+ config SUPPORT_TPL
+ bool
+
+ config SPL
+ bool
+ depends on SUPPORT_SPL
+ prompt "Enable SPL"
+ help
+ If you want to build SPL as well as the normal image, say Y.
+
+ config SPL_SYS_MALLOC_SIMPLE
+ bool
+ depends on SPL
+ prompt "Only use malloc_simple functions in the SPL"
+ help
+ Say Y here to only use the *_simple malloc functions from
+ malloc_simple.c, rather then using the versions from dlmalloc.c;
+ this will make the SPL binary smaller at the cost of more heap
+ usage as the *_simple malloc functions do not re-use free-ed mem.
+
+ config SPL_STACK_R
+ depends on SPL
+ bool "Enable SDRAM location for SPL stack"
+ help
+ SPL starts off execution in SRAM and thus typically has only a small
+ stack available. Since SPL sets up DRAM while in its board_init_f()
+ function, it is possible for the stack to move there before
+ board_init_r() is reached. This option enables a special SDRAM
+ location for the SPL stack. U-Boot SPL switches to this after
+ board_init_f() completes, and before board_init_r() starts.
+
+ config SPL_STACK_R_ADDR
+ depends on SPL_STACK_R
+ hex "SDRAM location for SPL stack"
+ help
+ Specify the address in SDRAM for the SPL stack. This will be set up
+ before board_init_r() is called.
+
+ config SPL_STACK_R_MALLOC_SIMPLE_LEN
+ depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
+ hex "Size of malloc_simple heap after switching to DRAM SPL stack"
+ default 0x100000
+ help
+ Specify the amount of the stack to use as memory pool for
+ malloc_simple after switching the stack to DRAM. This may be set
+ to give board_init_r() a larger heap then the initial heap in
+ SRAM which is limited to SYS_MALLOC_F_LEN bytes.
+
+ config SPL_SEPARATE_BSS
+ depends on SPL
+ bool "BSS section is in a different memory region from text"
+ help
+ Some platforms need a large BSS region in SPL and can provide this
+ because RAM is already set up. In this case BSS can be moved to RAM.
+ This option should then be enabled so that the correct device tree
+ location is used. Normally we put the device tree at the end of BSS
+ but with this option enabled, it goes at _image_binary_end.
+
+ config SPL_DISPLAY_PRINT
+ depends on SPL
+ bool "Display a board-specific message in SPL"
+ help
+ If this option is enabled, U-Boot will call the function
+ spl_display_print() immediately after displaying the SPL console
+ banner ("U-Boot SPL ..."). This function should be provided by
+ the board.
+
+ config TPL
+ bool
+ depends on SPL && SUPPORT_TPL
+ prompt "Enable TPL"
+ help
+ If you want to build TPL as well as the normal image and SPL, say Y.
+
+ config SPL_CRC32_SUPPORT
+ bool "Support CRC32"
+ depends on SPL_FIT
+ help
+ Enable this to support CRC32 in FIT images within SPL. This is a
+ 32-bit checksum value that can be used to verify images. This is
+ the least secure type of checksum, suitable for detected
+ accidental image corruption. For secure applications you should
+ consider SHA1 or SHA256.
+
+ config SPL_MD5_SUPPORT
+ bool "Support MD5"
+ depends on SPL_FIT
+ help
+ Enable this to support MD5 in FIT images within SPL. An MD5
+ checksum is a 128-bit hash value used to check that the image
+ contents have not been corrupted. Note that MD5 is not considered
+ secure as it is possible (with a brute-force attack) to adjust the
+ image while still retaining the same MD5 hash value. For secure
+ applications where images may be changed maliciously, you should
+ consider SHA1 or SHA256.
+
+ config SPL_SHA1_SUPPORT
+ bool "Support SHA1"
+ depends on SPL_FIT
+ help
+ Enable this to support SHA1 in FIT images within SPL. A SHA1
+ checksum is a 160-bit (20-byte) hash value used to check that the
+ image contents have not been corrupted or maliciously altered.
+ While SHA1 is fairly secure it is coming to the end of its life
+ due to the expanding computing power avaiable to brute-force
+ attacks. For more security, consider SHA256.
+
+ config SPL_SHA256_SUPPORT
+ bool "Support SHA256"
+ depends on SPL_FIT
+ help
+ Enable this to support SHA256 in FIT images within SPL. A SHA256
+ checksum is a 256-bit (32-byte) hash value used to check that the
+ image contents have not been corrupted. SHA256 is recommended for
+ use in secure applications since (as at 2016) there is no known
+ feasible attack that could produce a 'collision' with differing
+ input data. Use this for the highest security. Note that only the
+ SHA256 variant is supported: SHA512 and others are not currently
+ supported in U-Boot.
+
+ config SPL_CRYPTO_SUPPORT
+ bool "Support crypto drivers"
+ depends on SPL
+ help
+ Enable crypto drivers in SPL. These drivers can be used to
+ accelerate secure boot processing in secure applications. Enable
+ this option to build the drivers in drivers/crypto as part of an
+ SPL build.
+
+ config SPL_HASH_SUPPORT
+ bool "Support hashing drivers"
+ depends on SPL
+ help
+ Enable hashing drivers in SPL. These drivers can be used to
+ accelerate secure boot processing in secure applications. Enable
+ this option to build system-specific drivers for hash acceleration
+ as part of an SPL build.
+
+ config SPL_DMA_SUPPORT
+ bool "Support DMA drivers"
+ depends on SPL
+ help
+ Enable DMA (direct-memory-access) drivers in SPL. These drivers
+ can be used to handle memory-to-peripheral data transfer without
+ the CPU moving the data. Enable this option to build the drivers
+ in drivers/dma as part of an SPL build.
+
+ config SPL_DRIVERS_MISC_SUPPORT
+ bool "Support misc drivers"
+ depends on SPL
+ help
+ Enable miscellaneous drivers in SPL. These drivers perform various
+ tasks that don't fall nicely into other categories, Enable this
+ option to build the drivers in drivers/misc as part of an SPL
+ build, for those that support building in SPL (not all drivers do).
+
+ config SPL_ENV_SUPPORT
+ bool "Support an environment"
+ depends on SPL
+ help
+ Enable environment support in SPL. The U-Boot environment provides
+ a number of settings (essentially name/value pairs) which can
+ control many aspects of U-Boot's operation. Normally this is not
+ needed in SPL as it has a much simpler task with less
+ configuration. But some boards use this to support 'Falcon' boot
+ on EXT2 and FAT, where SPL boots directly into Linux without
+ starting U-Boot first. Enabling this option will make getenv()
+ and setenv() available in SPL.
+
+ config SPL_SAVEENV
+ bool "Support save environment"
+ depends on SPL && SPL_ENV_SUPPORT
+ help
+ Enable save environment support in SPL after setenv. By default
+ the saveenv option is not provided in SPL, but some boards need
+ this support in 'Falcon' boot, where SPL need to boot from
+ different images based on environment variable set by OS. For
+ example OS may set "reboot_image" environment variable to
+ "recovery" inorder to boot recovery image by SPL. The SPL read
+ "reboot_image" and act accordingly and change the reboot_image
+ to default mode using setenv and save the environemnt.
+
+ config SPL_ETH_SUPPORT
+ bool "Support Ethernet"
+ depends on SPL_ENV_SUPPORT
+ help
+ Enable access to the network subsystem and associated Ethernet
+ drivers in SPL. This permits SPL to load U-Boot over an Ethernet
+ link rather than from an on-board peripheral. Environment support
+ is required since the network stack uses a number of environment
+ variables. See also SPL_NET_SUPPORT.
+
+ config SPL_EXT_SUPPORT
+ bool "Support EXT filesystems"
+ depends on SPL
+ help
+ Enable support for EXT2/3/4 filesystems with SPL. This permits
+ U-Boot (or Linux in Falcon mode) to be loaded from an EXT
+ filesystem from within SPL. Support for the underlying block
+ device (e.g. MMC or USB) must be enabled separately.
+
+ config SPL_FAT_SUPPORT
+ bool "Support FAT filesystems"
+ depends on SPL
+ help
+ Enable support for FAT and VFAT filesystems with SPL. This
+ permits U-Boot (or Linux in Falcon mode) to be loaded from a FAT
+ filesystem from within SPL. Support for the underlying block
+ device (e.g. MMC or USB) must be enabled separately.
+
+ config SPL_FPGA_SUPPORT
+ bool "Support FPGAs"
+ depends on SPL
+ help
+ Enable support for FPGAs in SPL. Field-programmable Gate Arrays
+ provide software-configurable hardware which is typically used to
+ implement peripherals (such as UARTs, LCD displays, MMC) or
+ accelerate custom processing functions, such as image processing
+ or machine learning. Sometimes it is useful to program the FPGA
+ as early as possible during boot, and this option can enable that
+ within SPL.
+
++config SPL_FPGA_LOAD_ARGS_NAME
++ string "FPGA bitstream name"
++ depends on SPL_FPGA_SUPPORT
++ help
++ FPGA image file loaded in MMC/SD boot mode.
++
++config SPL_FPGA_LOAD_ADDR
++ hex "FPGA bitstream loading adddress"
++ depends on SPL_FPGA_LOAD_ARGS_NAME
++ default 0x1000000
++ help
++ Loading address for FPGA image in memory. On Xilinx Zynq this address
++ should be above 1M to make sure that devcfg can dma from this area.
++
+ config SPL_GPIO_SUPPORT
+ bool "Support GPIO"
+ depends on SPL
+ help
+ Enable support for GPIOs (General-purpose Input/Output) in SPL.
+ GPIOs allow U-Boot to read the state of an input line (high or
+ low) and set the state of an output line. This can be used to
+ drive LEDs, control power to various system parts and read user
+ input. GPIOs can be useful in SPL to enable a 'sign-of-life' LED,
+ for example. Enable this option to build the drivers in
+ drivers/gpio as part of an SPL build.
+
+ config SPL_I2C_SUPPORT
+ bool "Support I2C"
+ depends on SPL
+ help
+ Enable support for the I2C (Inter-Integrated Circuit) bus in SPL.
+ I2C works with a clock and data line which can be driven by a
+ one or more masters or slaves. It is a fairly complex bus but is
+ widely used as it only needs two lines for communication. Speeds of
+ 400kbps are typical but up to 3.4Mbps is supported by some
+ hardware. I2C can be useful in SPL to configure power management
+ ICs (PMICs) before raising the CPU clock speed, for example.
+ Enable this option to build the drivers in drivers/i2c as part of
+ an SPL build.
+
+ config SPL_LIBCOMMON_SUPPORT
+ bool "Support common libraries"
+ depends on SPL
+ help
+ Enable support for common U-Boot libraries within SPL. These
+ libraries include common code to deal with U-Boot images,
+ environment and USB, for example. This option is enabled on many
+ boards. Enable this option to build the code in common/ as part of
+ an SPL build.
+
+ config SPL_LIBDISK_SUPPORT
+ bool "Support disk paritions"
+ depends on SPL
+ help
+ Enable support for disk partitions within SPL. 'Disk' is something
+ of a misnomer as it includes non-spinning media such as flash (as
+ used in MMC and USB sticks). Partitions provide a way for a disk
+ to be split up into separate regions, with a partition table placed
+ at the start or end which describes the location and size of each
+ 'partition'. These partitions are typically uses as individual block
+ devices, typically with an EXT2 or FAT filesystem in each. This
+ option enables whatever partition support has been enabled in
+ U-Boot to also be used in SPL. It brings in the code in disk/.
+
+ config SPL_LIBGENERIC_SUPPORT
+ bool "Support generic libraries"
+ depends on SPL
+ help
+ Enable support for generic U-Boot libraries within SPL. These
+ libraries include generic code to deal with device tree, hashing,
+ printf(), compression and the like. This option is enabled on many
+ boards. Enable this option to build the code in lib/ as part of an
+ SPL build.
+
+ config SPL_MMC_SUPPORT
+ bool "Support MMC"
+ depends on SPL
+ help
+ Enable support for MMC (Multimedia Card) within SPL. This enables
+ the MMC protocol implementation and allows any enabled drivers to
+ be used within SPL. MMC can be used with or without disk partition
+ support depending on the application (SPL_LIBDISK_SUPPORT). Enable
+ this option to build the drivers in drivers/mmc as part of an SPL
+ build.
+
+ config SPL_MPC8XXX_INIT_DDR_SUPPORT
+ bool "Support MPC8XXX DDR init"
+ depends on SPL
+ help
+ Enable support for DDR-SDRAM (double-data-rate synchronous dynamic
+ random-access memory) on the MPC8XXX family within SPL. This
+ allows DRAM to be set up before loading U-Boot into that DRAM,
+ where it can run.
+
+ config SPL_MTD_SUPPORT
+ bool "Support MTD drivers"
+ depends on SPL
+ help
+ Enable support for MTD (Memory Technology Device) within SPL. MTD
+ provides a block interface over raw NAND and can also be used with
+ SPI flash. This allows SPL to load U-Boot from supported MTD
+ devices. See SPL_NAND_SUPPORT and SPL_ONENAND_SUPPORT for how
+ to enable specific MTD drivers.
+
+ config SPL_MUSB_NEW_SUPPORT
+ bool "Support new Mentor Graphics USB"
+ depends on SPL
+ help
+ Enable support for Mentor Graphics USB in SPL. This is a new
+ driver used by some boards. Enable this option to build
+ the drivers in drivers/usb/musb-new as part of an SPL build. The
+ old drivers are in drivers/usb/musb.
+
+ config SPL_NAND_SUPPORT
+ bool "Support NAND flash"
+ depends on SPL
+ help
+ Enable support for NAND (Negative AND) flash in SPL. NAND flash
+ can be used to allow SPL to load U-Boot from supported devices.
+ This enables the drivers in drivers/mtd/nand as part of an SPL
+ build.
+
+ config SPL_NET_SUPPORT
+ bool "Support networking"
+ depends on SPL
+ help
+ Enable support for network devices (such as Ethernet) in SPL.
+ This permits SPL to load U-Boot over a network link rather than
+ from an on-board peripheral. Environment support is required since
+ the network stack uses a number of environment variables. See also
+ SPL_ETH_SUPPORT.
+
+ if SPL_NET_SUPPORT
+ config SPL_NET_VCI_STRING
+ string "BOOTP Vendor Class Identifier string sent by SPL"
+ help
+ As defined by RFC 2132 the vendor class identifier field can be
+ sent by the client to identify the vendor type and configuration
+ of a client. This is often used in practice to allow for the DHCP
+ server to specify different files to load depending on if the ROM,
+ SPL or U-Boot itself makes the request
+ endif # if SPL_NET_SUPPORT
+
+ config SPL_NO_CPU_SUPPORT
+ bool "Drop CPU code in SPL"
+ depends on SPL
+ help
+ This is specific to the ARM926EJ-S CPU. It disables the standard
+ start.S start-up code, presumably so that a replacement can be
+ used on that CPU. You should not enable it unless you know what
+ you are doing.
+
+ config SPL_NOR_SUPPORT
+ bool "Support NOR flash"
+ depends on SPL
+ help
+ Enable support for loading U-Boot from memory-mapped NOR (Negative
+ OR) flash in SPL. NOR flash is slow to write but fast to read, and
+ a memory-mapped device makes it very easy to access. Loading from
+ NOR is typically achieved with just a memcpy().
+
+ config SPL_ONENAND_SUPPORT
+ bool "Support OneNAND flash"
+ depends on SPL
+ help
+ Enable support for OneNAND (Negative AND) flash in SPL. OneNAND is
+ a type of NAND flash and therefore can be used to allow SPL to
+ load U-Boot from supported devices. This enables the drivers in
+ drivers/mtd/onenand as part of an SPL build.
+
+ config SPL_OS_BOOT
+ bool "Activate Falcon Mode"
+ depends on SPL && !TI_SECURE_DEVICE
+ default n
+ help
+ Enable booting directly to an OS from SPL.
+ for more info read doc/README.falcon
+
+ if SPL_OS_BOOT
+ config SYS_OS_BASE
+ hex "addr, where OS is found"
+ depends on SPL && SPL_NOR_SUPPORT
+ help
+ Specify the address, where the OS image is found, which
+ gets booted.
+
+ endif # SPL_OS_BOOT
+
+ config SPL_POST_MEM_SUPPORT
+ bool "Support POST drivers"
+ depends on SPL
+ help
+ Enable support for POST (Power-on Self Test) in SPL. POST is a
+ procedure that checks that the hardware (CPU or board) appears to
+ be functionally correctly. It is a sanity check that can be
+ performed before booting. This enables the drivers in post/drivers
+ as part of an SPL build.
+
+ config SPL_POWER_SUPPORT
+ bool "Support power drivers"
+ depends on SPL
+ help
+ Enable support for power control in SPL. This includes support
+ for PMICs (Power-management Integrated Circuits) and some of the
+ features provided by PMICs. In particular, voltage regulators can
+ be used to enable/disable power and vary its voltage. That can be
+ useful in SPL to turn on boot peripherals and adjust CPU voltage
+ so that the clock speed can be increased. This enables the drivers
+ in drivers/power, drivers/power/pmic and drivers/power/regulator
+ as part of an SPL build.
+
+ config SPL_SATA_SUPPORT
+ bool "Support loading from SATA"
+ depends on SPL
+ help
+ Enable support for SATA (Serial AT attachment) in SPL. This allows
+ use of SATA devices such as hard drives and flash drivers for
+ loading U-Boot. SATA is used in higher-end embedded systems and
+ can provide higher performance than MMC , at somewhat higher
+ expense and power consumption. This enables loading from SATA
+ using a configured device.
+
+ config SPL_SERIAL_SUPPORT
+ bool "Support serial"
+ depends on SPL
+ help
+ Enable support for serial in SPL. This allows use of a serial UART
+ for displaying messages while SPL is running. It also brings in
+ printf() and panic() functions. This should normally be enabled
+ unless there are space reasons not to. Even then, consider
+ enabling USE_TINY_PRINTF which is a small printf() version.
+
+ config SPL_SPI_FLASH_SUPPORT
+ bool "Support SPI flash drivers"
+ depends on SPL
+ help
+ Enable support for using SPI flash in SPL, and loading U-Boot from
+ SPI flash. SPI flash (Serial Peripheral Bus flash) is named after
+ the SPI bus that is used to connect it to a system. It is a simple
+ but fast bidirectional 4-wire bus (clock, chip select and two data
+ lines). This enables the drivers in drivers/mtd/spi as part of an
+ SPL build. This normally requires SPL_SPI_SUPPORT.
+
+ config SPL_SPI_SUPPORT
+ bool "Support SPI drivers"
+ depends on SPL
+ help
+ Enable support for using SPI in SPL. This is used for connecting
+ to SPI flash for loading U-Boot. See SPL_SPI_FLASH_SUPPORT for
+ more details on that. The SPI driver provides the transport for
+ data between the SPI flash and the CPU. This option can be used to
+ enable SPI drivers that are needed for other purposes also, such
+ as a SPI PMIC.
+
+ config SPL_USBETH_SUPPORT
+ bool "Support USB Ethernet drivers"
+ depends on SPL
+ help
+ Enable access to the USB network subsystem and associated
+ drivers in SPL. This permits SPL to load U-Boot over a
+ USB-connected Ethernet link (such as a USB Ethernet dongle) rather
+ than from an onboard peripheral. Environment support is required
+ since the network stack uses a number of environment variables.
+ See also SPL_NET_SUPPORT and SPL_ETH_SUPPORT.
+
+ config SPL_USB_HOST_SUPPORT
+ bool "Support USB host drivers"
+ depends on SPL
+ help
+ Enable access to USB (Universal Serial Bus) host devices so that
+ SPL can load U-Boot from a connected USB peripheral, such as a USB
+ flash stick. While USB takes a little longer to start up than most
+ buses, it is very flexible since many different types of storage
+ device can be attached. This option enables the drivers in
+ drivers/usb/host as part of an SPL build.
+
+ config SPL_USB_SUPPORT
+ bool "Support loading from USB"
+ depends on SPL_USB_HOST_SUPPORT
+ help
+ Enable support for USB devices in SPL. This allows use of USB
+ devices such as hard drives and flash drivers for loading U-Boot.
+ The actual drivers are enabled separately using the normal U-Boot
+ config options. This enables loading from USB using a configured
+ device.
+
+ config SPL_WATCHDOG_SUPPORT
+ bool "Support watchdog drivers"
+ depends on SPL
+ help
+ Enable support for watchdog drivers in SPL. A watchdog is
+ typically a hardware peripheral which can reset the system when it
+ detects no activity for a while (such as a software crash). This
+ enables the drivers in drivers/watchdog as part of an SPL build.
+
+ config SPL_YMODEM_SUPPORT
+ bool "Support loading using Ymodem"
+ depends on SPL
+ help
+ While loading from serial is slow it can be a useful backup when
+ there is no other option. The Ymodem protocol provides a reliable
+ means of transmitting U-Boot over a serial line for using in SPL,
+ with a checksum to ensure correctness.
+
+ config TPL_ENV_SUPPORT
+ bool "Support an environment"
+ depends on TPL
+ help
+ Enable environment support in TPL. See SPL_ENV_SUPPORT for details.
+
+ config TPL_I2C_SUPPORT
+ bool "Support I2C"
+ depends on TPL
+ help
+ Enable support for the I2C bus in SPL. See SPL_I2C_SUPPORT for
+ details.
+
+ config TPL_LIBCOMMON_SUPPORT
+ bool "Support common libraries"
+ depends on TPL
+ help
+ Enable support for common U-Boot libraries within TPL. See
+ SPL_LIBCOMMON_SUPPORT for details.
+
+ config TPL_LIBGENERIC_SUPPORT
+ bool "Support generic libraries"
+ depends on TPL
+ help
+ Enable support for generic U-Boot libraries within TPL. See
+ SPL_LIBGENERIC_SUPPORT for details.
+
+ config TPL_MPC8XXX_INIT_DDR_SUPPORT
+ bool "Support MPC8XXX DDR init"
+ depends on TPL
+ help
+ Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See
+ SPL_MPC8XXX_INIT_DDR_SUPPORT for details.
+
+ config TPL_MMC_SUPPORT
+ bool "Support MMC"
+ depends on TPL
+ help
+ Enable support for MMC within TPL. See SPL_MMC_SUPPORT for details.
+
+ config TPL_NAND_SUPPORT
+ bool "Support NAND flash"
+ depends on TPL
+ help
+ Enable support for NAND in SPL. See SPL_NAND_SUPPORT for details.
+
+ config TPL_SERIAL_SUPPORT
+ bool "Support serial"
+ depends on TPL
+ help
+ Enable support for serial in SPL. See SPL_SERIAL_SUPPORT for
+ details.
+
+ config TPL_SPI_FLASH_SUPPORT
+ bool "Support SPI flash drivers"
+ depends on TPL
+ help
+ Enable support for using SPI flash in SPL. See SPL_SPI_FLASH_SUPPORT
+ for details.
+
+ config TPL_SPI_SUPPORT
+ bool "Support SPI drivers"
+ depends on TPL
+ help
+ Enable support for using SPI in SPL. See SPL_SPI_SUPPORT for
+ details.
+
+ endmenu
}
#endif
- static int mmc_load_fpga_image_fat(struct mmc *mmc)
+#ifdef CONFIG_SPL_FPGA_SUPPORT
- err = spl_load_image_fat(mmc_get_blk_desc(mmc),
++static int mmc_load_fpga_image_fat(struct spl_image_info *spl_image,
++ struct mmc *mmc)
+{
+ int err;
+ int devnum = 0;
+ const fpga_desc *const desc = fpga_get_desc(devnum);
+ xilinx_desc *desc_xilinx = desc->devdesc;
+
- return fpga_loadbitstream(devnum, (char *)spl_image.load_addr,
++ err = spl_load_image_fat(spl_image, mmc_get_blk_desc(mmc),
+ CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
+ CONFIG_SPL_FPGA_LOAD_ARGS_NAME);
+
+ if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("spl: error reading image %s, err - %d\n",
+ CONFIG_SPL_FPGA_LOAD_ARGS_NAME, err);
+#endif
+ return -1;
+ }
+#ifdef CONFIG_SPL_FPGA_BIT
- return fpga_load(devnum, (const void *)spl_image.load_addr,
++ return fpga_loadbitstream(devnum, (char *)spl_image->load_addr,
+ desc_xilinx->size, BIT_FULL);
+#else
++ return fpga_load(devnum, (const void *)spl_image->load_addr,
+ desc_xilinx->size, BIT_FULL);
+#endif
+}
+#endif
+
#ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
- int spl_mmc_do_fs_boot(struct mmc *mmc)
+ static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc)
{
int err = -ENOSYS;
case MMCSD_MODE_FS:
debug("spl: mmc boot mode: fs\n");
- mmc_load_fpga_image_fat(mmc);
+#ifdef CONFIG_SPL_FPGA_SUPPORT
- err = spl_mmc_do_fs_boot(mmc);
++ mmc_load_fpga_image_fat(spl_image, mmc);
+#endif
+
+ err = spl_mmc_do_fs_boot(spl_image, mmc);
if (!err)
return err;
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
- CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_NAND_ARASAN=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
--- /dev/null
- CONFIG_BLK=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="MINI_EMMC"
++# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
- CONFIG_DM_MMC_OPS=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="MINI_NAND"
++# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_NAND_ARASAN=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
+CONFIG_SYS_EXTRA_OPTIONS="MINI_QSPI"
++# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_EFI_LOADER is not set
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQMP_QSPI=y
CONFIG_ZYNQMP_USB=y
+ CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
- CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
- CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
--- /dev/null
- CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm017_dc3"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQMP_USB=y
++CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm017 dc3"
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3"
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm017 dc3"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
- CONFIG_BLK=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_SPL=y
++CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_DM_MMC_OPS=y
++CONFIG_FPGA_XILINX=y
++CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_NAND_ARASAN=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQMP_USB=y
++CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevB"
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100"
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevB"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
- CONFIG_BLK=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_SPL=y
++CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_DM_MMC_OPS=y
++CONFIG_FPGA_XILINX=y
++CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/zynqmp-zcu100-revA/regs.txt"
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_ZYNQMP_USB=y
++CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevA"
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revA"
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevA"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
- CONFIG_BLK=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_SPL=y
++CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_DM_MMC_OPS=y
++CONFIG_FPGA_XILINX=y
++CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_PMUFW_INIT_FILE="board/xilinx/zynqmp/pmufw.bin"
+CONFIG_ZYNQMP_QSPI=y
CONFIG_ZYNQMP_USB=y
+ CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
- CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+ CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_BLK=y
+ CONFIG_DFU_RAM=y
+ CONFIG_FPGA_XILINX=y
+ CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
- CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQMP_QSPI=y
CONFIG_ZYNQMP_USB=y
+ CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
- CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+ CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_BLK=y
+ CONFIG_DFU_RAM=y
+ CONFIG_FPGA_XILINX=y
+ CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
- CONFIG_DM_MMC_OPS=y
CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
--- /dev/null
- CONFIG_SPL=y
- CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu106"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_ZYNQMP_USB=y
++CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU106"
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106"
- CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU106"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
- CONFIG_BLK=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_SPL=y
++CONFIG_SPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_DM_MMC_OPS=y
++CONFIG_FPGA_XILINX=y
++CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- CONFIG_SPL=y
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_NO_FLASH=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_DFU_MMC=y
+ CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_DFU_MMC=y
+ CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
--- /dev/null
- CONFIG_SPL=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_NO_FLASH=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_SPL=y
++CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_ZYNQ_AES=y
+CONFIG_CMD_ZYNQ_RSA=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
++CONFIG_DFU_MMC=y
++CONFIG_DFU_RAM=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
- CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_DFU_MMC=y
+ CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_DFU_MMC=y
+ CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
- CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+ # CONFIG_DISPLAY_CPUINFO is not set
+ CONFIG_SPL=y
+ CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_DFU_MMC=y
+ CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_DFU_MMC=y
+ CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
setting up clocks within SPL, and allows the same drivers to be
used as U-Boot proper.
+ config CLK_BOSTON
+ def_bool y if TARGET_BOSTON
+ depends on CLK
+ select REGMAP
+ select SYSCON
+ help
+ Enable this to support the clocks
+
+config CLK_ZYNQMP
+ bool "Enable clock driver support for ZynqMP"
+ depends on ARCH_ZYNQMP
+ help
+ This clock driver adds support for clock realted settings for
+ ZynqMP platform.
+
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
controller. This uses the hardware ECC for read and
write operations.
+config NAND_ZYNQ
+ bool "Support for Nand on Zynq SoC"
+ help
+ This enables Nand driver support for Nand controller
+ on Zynq SoC.
+
+ config NAND_MXS
+ bool "MXS NAND support"
+ depends on MX6
+ help
+ This enables NAND driver for the NAND flash controller on the
+ MXS processors.
+
comment "Generic NAND options"
# Enhance depends when converting drivers to Kconfig which use this config
--- /dev/null
- #include <asm/errno.h>
+/*
+ * Xilinx Zynq NAND Flash Controller Driver
+ * This driver is based on plat_nand.c and mxc_nand.c drivers
+ *
+ * Copyright (C) 2009 - 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
++#include <linux/errno.h>
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand_ecc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+/* The NAND flash driver defines */
+#define ZYNQ_NAND_CMD_PHASE 1 /* End command valid in command phase */
+#define ZYNQ_NAND_DATA_PHASE 2 /* End command valid in data phase */
+#define ZYNQ_NAND_ECC_SIZE 512 /* Size of data for ECC operation */
+
+/* Flash memory controller operating parameters */
+#define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \
+ (0x1 << 4) | /* Clear interrupt */ \
+ (0x1 << 6)) /* Disable ECC interrupt */
+
+/* Assuming 50MHz clock (20ns cycle time) and 3V operation */
+#define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
+ (0x2 << 17) | /* t_ar from nand_cycles */ \
+ (0x1 << 14) | /* t_clr from nand_cycles */ \
+ (0x3 << 11) | /* t_wp from nand_cycles */ \
+ (0x2 << 8) | /* t_rea from nand_cycles */ \
+ (0x5 << 4) | /* t_wc from nand_cycles */ \
+ (0x5 << 0)) /* t_rc from nand_cycles */
+
+#define ZYNQ_NAND_SET_OPMODE 0x0
+
+#define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
+ (0x2 << 21)) /* UpdateRegs operation */
+
+#define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
+ (0x1 << 4) | /* ECC read at end of page */ \
+ (0x0 << 5)) /* No Jumping */
+
+#define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
+ (0x00 << 8) | /* Read command */ \
+ (0x30 << 16) | /* Read End command */ \
+ (0x1 << 24)) /* Read End command calid */
+
+#define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
+ (0x05 << 8) | /* Read col change cmd */ \
+ (0xE0 << 16) | /* Read col change end cmd */ \
+ (0x1 << 24)) /* Read col change
+ end cmd valid */
+/* AXI Address definitions */
+#define START_CMD_SHIFT 3
+#define END_CMD_SHIFT 11
+#define END_CMD_VALID_SHIFT 20
+#define ADDR_CYCLES_SHIFT 21
+#define CLEAR_CS_SHIFT 21
+#define ECC_LAST_SHIFT 10
+#define COMMAND_PHASE (0 << 19)
+#define DATA_PHASE (1 << 19)
+
+#define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */
+#define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */
+
+/* ECC block registers bit position and bit mask */
+#define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
+#define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
+
+#define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F
+#define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0
+
+/* NAND MIO buswidth count*/
+#define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13
+#define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8
+
+/* NAND buswidth */
+enum zynq_nand_bus_width {
+ NAND_BW_UNKNOWN = -1,
+ NAND_BW_8BIT,
+ NAND_BW_16BIT,
+};
+
+/* SMC register set */
+struct zynq_nand_smc_regs {
+ u32 csr; /* 0x00 */
+ u32 reserved0[2];
+ u32 cfr; /* 0x0C */
+ u32 dcr; /* 0x10 */
+ u32 scr; /* 0x14 */
+ u32 sor; /* 0x18 */
+ u32 reserved1[249];
+ u32 esr; /* 0x400 */
+ u32 emcr; /* 0x404 */
+ u32 emcmd1r; /* 0x408 */
+ u32 emcmd2r; /* 0x40C */
+ u32 reserved2[2];
+ u32 eval0r; /* 0x418 */
+};
+
+#define zynq_nand_smc_base ((struct zynq_nand_smc_regs *)ZYNQ_SMC_BASEADDR)
+
+/*
+ * struct zynq_nand_command_format - Defines NAND flash command format
+ * @start_cmd: First cycle command (Start command)
+ * @end_cmd: Second cycle command (Last command)
+ * @addr_cycles: Number of address cycles required to send the address
+ * @end_cmd_valid: The second cycle command is valid for cmd or data phase
+ */
+struct zynq_nand_command_format {
+ int start_cmd;
+ int end_cmd;
+ u8 addr_cycles;
+ u8 end_cmd_valid;
+};
+
+/*
+ * struct zynq_nand_info - Defines the NAND flash driver instance
+ * @parts: Pointer to the mtd_partition structure
+ * @nand_base: Virtual address of the NAND flash device
+ * @end_cmd_pending: End command is pending
+ * @end_cmd: End command
+ */
+struct zynq_nand_info {
+#ifdef CONFIG_MTD_PARTITIONS
+ struct mtd_partition *parts;
+#endif
+ void __iomem *nand_base;
+ unsigned long end_cmd_pending;
+ unsigned long end_cmd;
+};
+
+#define ONDIE_ECC_FEATURE_ADDR 0x90
+
+/* The NAND flash operations command format */
+static const struct zynq_nand_command_format zynq_nand_commands[] = {
+ {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
+ {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
+ {NAND_CMD_READID, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+ {NAND_CMD_STATUS, NAND_CMD_NONE, 0, NAND_CMD_NONE},
+ {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
+ {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, NAND_CMD_NONE},
+ {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
+ {NAND_CMD_RESET, NAND_CMD_NONE, 0, NAND_CMD_NONE},
+ {NAND_CMD_PARAM, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+ {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+ {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE},
+ {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
+ /* Add all the flash commands supported by the flash device and Linux
+ * The cache program command is not supported by driver because driver
+ * cant differentiate between page program and cached page program from
+ * start command, these commands can be differentiated through end
+ * command, which doesn't fit in to the driver design. The cache program
+ * command is not supported by NAND subsystem also, look at 1612 line
+ * number (in nand_write_page function) of nand_base.c file.
+ * {NAND_CMD_SEQIN, NAND_CMD_CACHEDPROG, 5, ZYNQ_NAND_YES}
+ */
+};
+
+/* Define default oob placement schemes for large and small page devices */
+static struct nand_ecclayout nand_oob_16 = {
+ .eccbytes = 3,
+ .eccpos = {13, 14, 15},
+ .oobfree = {
+ { .offset = 0, .length = 12 }
+ }
+};
+
+static struct nand_ecclayout nand_oob_64 = {
+ .eccbytes = 12,
+ .eccpos = {
+ 52, 53, 54, 55, 56, 57,
+ 58, 59, 60, 61, 62, 63},
+ .oobfree = {
+ { .offset = 2, .length = 50 }
+ }
+};
+
+static struct nand_ecclayout ondie_nand_oob_64 = {
+ .eccbytes = 32,
+
+ .eccpos = {
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 56, 57, 58, 59, 60, 61, 62, 63
+ },
+
+ .oobfree = {
+ { .offset = 4, .length = 4 },
+ { .offset = 20, .length = 4 },
+ { .offset = 36, .length = 4 },
+ { .offset = 52, .length = 4 }
+ }
+};
+
+/* Generic flash bbt decriptors */
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 4,
+ .len = 4,
+ .veroffs = 20,
+ .maxblocks = 4,
+ .pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 4,
+ .len = 4,
+ .veroffs = 20,
+ .maxblocks = 4,
+ .pattern = mirror_pattern
+};
+
+/*
+ * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
+ *
+ * returns: status for command completion, -1 for Timeout
+ */
+static int zynq_nand_waitfor_ecc_completion(void)
+{
+ unsigned long timeout;
+ u32 status;
+
+ /* Wait max 10ms */
+ timeout = 10;
+ status = readl(&zynq_nand_smc_base->esr);
+ while (status & ZYNQ_NAND_ECC_BUSY) {
+ status = readl(&zynq_nand_smc_base->esr);
+ if (timeout == 0)
+ return -1;
+ timeout--;
+ udelay(1);
+ }
+
+ return status;
+}
+
+/*
+ * zynq_nand_init_nand_flash - Initialize NAND controller
+ * @option: Device property flags
+ *
+ * This function initializes the NAND flash interface on the NAND controller.
+ *
+ * returns: 0 on success or error value on failure
+ */
+static int zynq_nand_init_nand_flash(int option)
+{
+ u32 status;
+
+ /* disable interrupts */
+ writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
+ /* Initialize the NAND interface by setting cycles and operation mode */
+ writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
+ if (option & NAND_BUSWIDTH_16)
+ writel((ZYNQ_NAND_SET_OPMODE | 0x1), &zynq_nand_smc_base->sor);
+ else
+ writel(ZYNQ_NAND_SET_OPMODE, &zynq_nand_smc_base->sor);
+
+ writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
+
+ /* Wait till the ECC operation is complete */
+ status = zynq_nand_waitfor_ecc_completion();
+ if (status < 0) {
+ printf("%s: Timeout\n", __func__);
+ return status;
+ }
+
+ /* Set the command1 and command2 register */
+ writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
+ writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
+
+ return 0;
+}
+
+/*
+ * zynq_nand_calculate_hwecc - Calculate Hardware ECC
+ * @mtd: Pointer to the mtd_info structure
+ * @data: Pointer to the page data
+ * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored
+ *
+ * This function retrieves the Hardware ECC data from the controller and returns
+ * ECC data back to the MTD subsystem.
+ *
+ * returns: 0 on success or error value on failure
+ */
+static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
+ u8 *ecc_code)
+{
+ u32 ecc_value = 0;
+ u8 ecc_reg, ecc_byte;
+ u32 ecc_status;
+
+ /* Wait till the ECC operation is complete */
+ ecc_status = zynq_nand_waitfor_ecc_completion();
+ if (ecc_status < 0) {
+ printf("%s: Timeout\n", __func__);
+ return ecc_status;
+ }
+
+ for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
+ /* Read ECC value for each block */
+ ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
+ ecc_status = (ecc_value >> 24) & 0xFF;
+ /* ECC value valid */
+ if (ecc_status & 0x40) {
+ for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
+ /* Copy ECC bytes to MTD buffer */
+ *ecc_code = ecc_value & 0xFF;
+ ecc_value = ecc_value >> 8;
+ ecc_code++;
+ }
+ } else {
+ debug("%s: ecc status failed\n", __func__);
+ }
+ }
+ return 0;
+}
+
+/*
+ * onehot - onehot function
+ * @value: value to check for onehot
+ *
+ * This function checks whether a value is onehot or not.
+ * onehot is if and only if onebit is set.
+ *
+ */
+static int onehot(unsigned short value)
+{
+ return ((value & (value-1)) == 0);
+}
+
+/*
+ * zynq_nand_correct_data - ECC correction function
+ * @mtd: Pointer to the mtd_info structure
+ * @buf: Pointer to the page data
+ * @read_ecc: Pointer to the ECC value read from spare data area
+ * @calc_ecc: Pointer to the calculated ECC value
+ *
+ * This function corrects the ECC single bit errors & detects 2-bit errors.
+ *
+ * returns: 0 if no ECC errors found
+ * 1 if single bit error found and corrected.
+ * -1 if multiple ECC errors found.
+ */
+static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
+ unsigned char *read_ecc, unsigned char *calc_ecc)
+{
+ unsigned char bit_addr;
+ unsigned int byte_addr;
+ unsigned short ecc_odd, ecc_even;
+ unsigned short read_ecc_lower, read_ecc_upper;
+ unsigned short calc_ecc_lower, calc_ecc_upper;
+
+ read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
+ read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
+
+ calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
+ calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
+
+ ecc_odd = read_ecc_lower ^ calc_ecc_lower;
+ ecc_even = read_ecc_upper ^ calc_ecc_upper;
+
+ if ((ecc_odd == 0) && (ecc_even == 0))
+ return 0; /* no error */
+ else if (ecc_odd == (~ecc_even & 0xfff)) {
+ /* bits [11:3] of error code is byte offset */
+ byte_addr = (ecc_odd >> 3) & 0x1ff;
+ /* bits [2:0] of error code is bit offset */
+ bit_addr = ecc_odd & 0x7;
+ /* Toggling error bit */
+ buf[byte_addr] ^= (1 << bit_addr);
+ return 1;
+ } else if (onehot(ecc_odd | ecc_even) == 1) {
+ return 1; /* one error in parity */
+ } else {
+ return -1; /* Uncorrectable error */
+ }
+}
+
+/*
+ * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to read
+ * @sndcmd: flag whether to issue read command or not
+ */
+static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ unsigned long data_width = 4;
+ unsigned long data_phase_addr = 0;
+ u8 *p;
+
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+
+ p = chip->oob_poi;
+ chip->read_buf(mtd, p, (mtd->oobsize - data_width));
+ p += (mtd->oobsize - data_width);
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+ chip->read_buf(mtd, p, data_width);
+
+ return 0;
+}
+
+/*
+ * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to write
+ */
+static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ int status = 0;
+ const u8 *buf = chip->oob_poi;
+ unsigned long data_width = 4;
+ unsigned long data_phase_addr = 0;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+ chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
+ buf += (mtd->oobsize - data_width);
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+ chip->write_buf(mtd, buf, data_width);
+
+ /* Send command to program the OOB data */
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/*
+ * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to read
+ */
+static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ u8 *buf, int oob_required, int page)
+{
+ unsigned long data_width = 4;
+ unsigned long data_phase_addr = 0;
+ u8 *p;
+
+ chip->read_buf(mtd, buf, mtd->writesize);
+
+ p = chip->oob_poi;
+ chip->read_buf(mtd, p, (mtd->oobsize - data_width));
+ p += (mtd->oobsize - data_width);
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+
+ chip->read_buf(mtd, p, data_width);
+ return 0;
+}
+
+static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
+ struct nand_chip *chip, u8 *buf, int oob_required, int page)
+{
+ chip->read_buf(mtd, buf, mtd->writesize);
+ return 0;
+}
+
+static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, uint32_t offs,
+ uint32_t len, uint8_t *buf, int page)
+{
+ if (offs != 0) {
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offs, -1);
+ buf += offs;
+ }
+
+ chip->read_buf(mtd, buf, len);
+ return 0;
+}
+
+/*
+ * zynq_nand_write_page_raw - [Intern] raw page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ */
+static int zynq_nand_write_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, const u8 *buf, int oob_required, int page)
+{
+ unsigned long data_width = 4;
+ unsigned long data_phase_addr = 0;
+ u8 *p;
+
+ chip->write_buf(mtd, buf, mtd->writesize);
+
+ p = chip->oob_poi;
+ chip->write_buf(mtd, p, (mtd->oobsize - data_width));
+ p += (mtd->oobsize - data_width);
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+
+ chip->write_buf(mtd, p, data_width);
+
+ return 0;
+}
+
+/*
+ * nand_write_page_hwecc - Hardware ECC based page write function
+ * @mtd: Pointer to the mtd info structure
+ * @chip: Pointer to the NAND chip info structure
+ * @buf: Pointer to the data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ *
+ * This functions writes data and hardware generated ECC values in to the page.
+ */
+static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const u8 *buf, int oob_required, int page)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccsteps = chip->ecc.steps;
+ u8 *ecc_calc = chip->buffers->ecccalc;
+ const u8 *p = buf;
+ u32 *eccpos = chip->ecc.layout->eccpos;
+ unsigned long data_phase_addr = 0;
+ unsigned long data_width = 4;
+ u8 *oob_ptr;
+
+ for (; (eccsteps - 1); eccsteps--) {
+ chip->write_buf(mtd, p, eccsize);
+ p += eccsize;
+ }
+ chip->write_buf(mtd, p, (eccsize - data_width));
+ p += (eccsize - data_width);
+
+ /* Set ECC Last bit to 1 */
+ data_phase_addr = (unsigned long) chip->IO_ADDR_W;
+ data_phase_addr |= ZYNQ_NAND_ECC_LAST;
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+ chip->write_buf(mtd, p, data_width);
+
+ /* Wait for ECC to be calculated and read the error values */
+ p = buf;
+ chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+
+ for (i = 0; i < chip->ecc.total; i++)
+ chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
+
+ /* Clear ECC last bit */
+ data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+ data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+
+ /* Write the spare area with ECC bytes */
+ oob_ptr = chip->oob_poi;
+ chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
+
+ data_phase_addr = (unsigned long)chip->IO_ADDR_W;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
+ chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
+ oob_ptr += (mtd->oobsize - data_width);
+ chip->write_buf(mtd, oob_ptr, data_width);
+
+ return 0;
+}
+
+/*
+ * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
+ * write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ */
+static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const u8 *buf, int oob_required, int page)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ u8 *ecc_calc = chip->buffers->ecccalc;
+ const u8 *p = buf;
+ u32 *eccpos = chip->ecc.layout->eccpos;
+
+ /* Software ecc calculation */
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ for (i = 0; i < chip->ecc.total; i++)
+ chip->oob_poi[eccpos[i]] = ecc_calc[i];
+
+ return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
+}
+
+/*
+ * nand_read_page_hwecc - Hardware ECC based page read function
+ * @mtd: Pointer to the mtd info structure
+ * @chip: Pointer to the NAND chip info structure
+ * @buf: Pointer to the buffer to store read data
+ * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to read
+ *
+ * This functions reads data and checks the data integrity by comparing hardware
+ * generated ECC values and read ECC values from spare area.
+ *
+ * returns: 0 always and updates ECC operation status in to MTD structure
+ */
+static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, u8 *buf, int oob_required, int page)
+{
+ int i, stat, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ u8 *p = buf;
+ u8 *ecc_calc = chip->buffers->ecccalc;
+ u8 *ecc_code = chip->buffers->ecccode;
+ u32 *eccpos = chip->ecc.layout->eccpos;
+ unsigned long data_phase_addr = 0;
+ unsigned long data_width = 4;
+ u8 *oob_ptr;
+
+ for (; (eccsteps - 1); eccsteps--) {
+ chip->read_buf(mtd, p, eccsize);
+ p += eccsize;
+ }
+ chip->read_buf(mtd, p, (eccsize - data_width));
+ p += (eccsize - data_width);
+
+ /* Set ECC Last bit to 1 */
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr |= ZYNQ_NAND_ECC_LAST;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+ chip->read_buf(mtd, p, data_width);
+
+ /* Read the calculated ECC value */
+ p = buf;
+ chip->ecc.calculate(mtd, p, &ecc_calc[0]);
+
+ /* Clear ECC last bit */
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+
+ /* Read the stored ECC value */
+ oob_ptr = chip->oob_poi;
+ chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
+
+ /* de-assert chip select */
+ data_phase_addr = (unsigned long)chip->IO_ADDR_R;
+ data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+
+ oob_ptr += (mtd->oobsize - data_width);
+ chip->read_buf(mtd, oob_ptr, data_width);
+
+ for (i = 0; i < chip->ecc.total; i++)
+ ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
+
+ eccsteps = chip->ecc.steps;
+ p = buf;
+
+ /* Check ECC error for all blocks and correct if it is correctable */
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+ }
+ return 0;
+}
+
+/*
+ * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
+ * read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @page: page number to read
+ */
+static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
+ struct nand_chip *chip, u8 *buf, int oob_required, int page)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ u8 *p = buf;
+ u8 *ecc_calc = chip->buffers->ecccalc;
+ u8 *ecc_code = chip->buffers->ecccode;
+ u32 *eccpos = chip->ecc.layout->eccpos;
+
+ chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ for (i = 0; i < chip->ecc.total; i++)
+ ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+ eccsteps = chip->ecc.steps;
+ p = buf;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+ }
+ return 0;
+}
+
+/*
+ * zynq_nand_select_chip - Select the flash device
+ * @mtd: Pointer to the mtd_info structure
+ * @chip: Chip number to be selected
+ *
+ * This function is empty as the NAND controller handles chip select line
+ * internally based on the chip address passed in command and data phase.
+ */
+static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ return;
+}
+
+/*
+ * zynq_nand_cmd_function - Send command to NAND device
+ * @mtd: Pointer to the mtd_info structure
+ * @command: The command to be sent to the flash device
+ * @column: The column address for this command, -1 if none
+ * @page_addr: The page address for this command, -1 if none
+ */
+static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ const struct zynq_nand_command_format *curr_cmd = NULL;
+ u8 addr_cycles = 0;
+ struct zynq_nand_info *xnand;
+ void *cmd_addr;
+ unsigned long cmd_data = 0;
+ unsigned long cmd_phase_addr = 0;
+ unsigned long data_phase_addr = 0;
+ unsigned long end_cmd = 0;
+ unsigned long end_cmd_valid = 0;
+ unsigned long i;
+
+ xnand = nand_get_controller_data(chip);
+ if (xnand->end_cmd_pending) {
+ /* Check for end command if this command request is same as the
+ * pending command then return
+ */
+ if (xnand->end_cmd == command) {
+ xnand->end_cmd = 0;
+ xnand->end_cmd_pending = 0;
+ return;
+ }
+ }
+
+ /* Emulate NAND_CMD_READOOB for large page device */
+ if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
+ (command == NAND_CMD_READOOB)) {
+ column += mtd->writesize;
+ command = NAND_CMD_READ0;
+ }
+
+ /* Get the command format */
+ for (i = 0; (zynq_nand_commands[i].start_cmd != NAND_CMD_NONE ||
+ zynq_nand_commands[i].end_cmd != NAND_CMD_NONE); i++) {
+ if (command == zynq_nand_commands[i].start_cmd)
+ curr_cmd = &zynq_nand_commands[i];
+ }
+ if (curr_cmd == NULL)
+ return;
+
+ /* Clear interrupt */
+ writel((1 << 4), &zynq_nand_smc_base->cfr);
+
+ /* Get the command phase address */
+ if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
+ end_cmd_valid = 1;
+
+ if (curr_cmd->end_cmd == NAND_CMD_NONE)
+ end_cmd = 0x0;
+ else
+ end_cmd = curr_cmd->end_cmd;
+
+ if ((command == NAND_CMD_READ0) ||
+ (command == NAND_CMD_SEQIN)) {
+ addr_cycles = chip->onfi_params.addr_cycles &
+ ZYNQ_NAND_ROW_ADDR_CYCL_MASK;
+ addr_cycles += ((chip->onfi_params.addr_cycles &
+ ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4);
+ } else {
+ addr_cycles = curr_cmd->addr_cycles;
+ }
+
+ cmd_phase_addr = (unsigned long)xnand->nand_base |
+ (addr_cycles << ADDR_CYCLES_SHIFT) |
+ (end_cmd_valid << END_CMD_VALID_SHIFT) |
+ (COMMAND_PHASE) |
+ (end_cmd << END_CMD_SHIFT) |
+ (curr_cmd->start_cmd << START_CMD_SHIFT);
+
+ cmd_addr = (void __iomem *)cmd_phase_addr;
+
+ /* Get the data phase address */
+ end_cmd_valid = 0;
+
+ data_phase_addr = (unsigned long)xnand->nand_base |
+ (0x0 << CLEAR_CS_SHIFT) |
+ (end_cmd_valid << END_CMD_VALID_SHIFT) |
+ (DATA_PHASE) |
+ (end_cmd << END_CMD_SHIFT) |
+ (0x0 << ECC_LAST_SHIFT);
+
+ chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
+ chip->IO_ADDR_W = chip->IO_ADDR_R;
+
+ /* Command phase AXI Read & Write */
+ if (column != -1 && page_addr != -1) {
+ /* Adjust columns for 16 bit bus width */
+ if (chip->options & NAND_BUSWIDTH_16)
+ column >>= 1;
+ cmd_data = column;
+ if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
+ cmd_data |= page_addr << 16;
+ /* Another address cycle for devices > 128MiB */
+ if (chip->chipsize > (128 << 20)) {
+ writel(cmd_data, cmd_addr);
+ cmd_data = (page_addr >> 16);
+ }
+ } else {
+ cmd_data |= page_addr << 8;
+ }
+ }
+ /* Erase */
+ else if (page_addr != -1)
+ cmd_data = page_addr;
+ /* Change read/write column, read id etc */
+ else if (column != -1) {
+ /* Adjust columns for 16 bit bus width */
+ if ((chip->options & NAND_BUSWIDTH_16) &&
+ ((command == NAND_CMD_READ0) ||
+ (command == NAND_CMD_SEQIN) ||
+ (command == NAND_CMD_RNDOUT) ||
+ (command == NAND_CMD_RNDIN)))
+ column >>= 1;
+ cmd_data = column;
+ } else
+ ;
+
+ writel(cmd_data, cmd_addr);
+
+ if (curr_cmd->end_cmd_valid) {
+ xnand->end_cmd = curr_cmd->end_cmd;
+ xnand->end_cmd_pending = 1;
+ }
+
+ ndelay(100);
+
+ if ((command == NAND_CMD_READ0) ||
+ (command == NAND_CMD_RESET) ||
+ (command == NAND_CMD_PARAM) ||
+ (command == NAND_CMD_GET_FEATURES)) {
+ while (!chip->dev_ready(mtd))
+ ;
+ return;
+ }
+}
+
+/*
+ * zynq_nand_read_buf - read chip data into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
+static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ const u32 *nand = chip->IO_ADDR_R;
+
+ /* Make sure that buf is 32 bit aligned */
+ if (((int)buf & 0x3) != 0) {
+ if (((int)buf & 0x1) != 0) {
+ if (len) {
+ *buf = readb(nand);
+ buf += 1;
+ len--;
+ }
+ }
+
+ if (((int)buf & 0x3) != 0) {
+ if (len >= 2) {
+ *(u16 *)buf = readw(nand);
+ buf += 2;
+ len -= 2;
+ }
+ }
+ }
+
+ /* copy aligned data */
+ while (len >= 4) {
+ *(u32 *)buf = readl(nand);
+ buf += 4;
+ len -= 4;
+ }
+
+ /* mop up any remaining bytes */
+ if (len) {
+ if (len >= 2) {
+ *(u16 *)buf = readw(nand);
+ buf += 2;
+ len -= 2;
+ }
+
+ if (len)
+ *buf = readb(nand);
+ }
+}
+
+/*
+ * zynq_nand_write_buf - write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ const u32 *nand = chip->IO_ADDR_W;
+
+ /* Make sure that buf is 32 bit aligned */
+ if (((int)buf & 0x3) != 0) {
+ if (((int)buf & 0x1) != 0) {
+ if (len) {
+ writeb(*buf, nand);
+ buf += 1;
+ len--;
+ }
+ }
+
+ if (((int)buf & 0x3) != 0) {
+ if (len >= 2) {
+ writew(*(u16 *)buf, nand);
+ buf += 2;
+ len -= 2;
+ }
+ }
+ }
+
+ /* copy aligned data */
+ while (len >= 4) {
+ writel(*(u32 *)buf, nand);
+ buf += 4;
+ len -= 4;
+ }
+
+ /* mop up any remaining bytes */
+ if (len) {
+ if (len >= 2) {
+ writew(*(u16 *)buf, nand);
+ buf += 2;
+ len -= 2;
+ }
+
+ if (len)
+ writeb(*buf, nand);
+ }
+}
+
+/*
+ * zynq_nand_device_ready - Check device ready/busy line
+ * @mtd: Pointer to the mtd_info structure
+ *
+ * returns: 0 on busy or 1 on ready state
+ */
+static int zynq_nand_device_ready(struct mtd_info *mtd)
+{
+ /* Check the raw_int_status1 bit */
+ if ((readl(&zynq_nand_smc_base->csr)) & 0x40) {
+ /* Clear the interrupt condition */
+ writel((1 << 4), &zynq_nand_smc_base->cfr);
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * zynq_nand_check_is_16bit_bw_flash - checking for 16 or 8 bit buswidth nand
+ *
+ * This function will check nand buswidth whether it supports 16 or 8 bit
+ * based on the MIO configuration done by FSBL.
+ *
+ * User needs to correctly configure the MIO's based on the
+ * buswidth supported by the nand flash which is present on the board.
+ *
+ * function will return -1, if there is no MIO configuration for
+ * nand flash.
+ */
+static int zynq_nand_check_is_16bit_bw_flash(void)
+{
+ int is_16bit_bw = NAND_BW_UNKNOWN;
+ int mio_num_8bit = 0, mio_num_16bit = 0;
+
+ mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
+ if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
+ is_16bit_bw = NAND_BW_8BIT;
+
+ mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
+ if ((mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT) &&
+ (mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT))
+ is_16bit_bw = NAND_BW_16BIT;
+
+ return is_16bit_bw;
+}
+
+static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+{
+ struct zynq_nand_info *xnand;
+ struct mtd_info *mtd;
+ unsigned long ecc_page_size;
+ int err = -1;
+ u8 maf_id, dev_id, i;
+ u8 get_feature[4];
+ u8 set_feature[4] = {0x08, 0x00, 0x00, 0x00};
+ unsigned long ecc_cfg;
+ int ondie_ecc_enabled = 0;
+ int is_16bit_bw;
+
+ xnand = calloc(1, sizeof(struct zynq_nand_info));
+ if (!xnand) {
+ printf("%s: failed to allocate\n", __func__);
+ goto free;
+ }
+
+ xnand->nand_base = (void *)ZYNQ_NAND_BASEADDR;
+ mtd = nand_to_mtd(nand_chip);
+ nand_set_controller_data(nand_chip, xnand);
+
+ /* Set address of NAND IO lines */
+ nand_chip->IO_ADDR_R = xnand->nand_base;
+ nand_chip->IO_ADDR_W = xnand->nand_base;
+
+ /* Set the driver entry points for MTD */
+ nand_chip->cmdfunc = zynq_nand_cmd_function;
+ nand_chip->dev_ready = zynq_nand_device_ready;
+ nand_chip->select_chip = zynq_nand_select_chip;
+
+ /* If we don't set this delay driver sets 20us by default */
+ nand_chip->chip_delay = 30;
+
+ /* Buffer read/write routines */
+ nand_chip->read_buf = zynq_nand_read_buf;
+ nand_chip->write_buf = zynq_nand_write_buf;
+
+ /* Check the NAND buswidth */
+ /* FIXME this will be changed by using NAND_BUSWIDTH_AUTO */
+ is_16bit_bw = zynq_nand_check_is_16bit_bw_flash();
+ if (is_16bit_bw == NAND_BW_UNKNOWN) {
+ printf("%s: Unable detect NAND based on MIO settings\n",
+ __func__);
+ goto free;
+ } else if (is_16bit_bw == NAND_BW_16BIT) {
+ nand_chip->options = NAND_BUSWIDTH_16;
+ }
+ nand_chip->bbt_options = NAND_BBT_USE_FLASH;
+
+ /* Initialize the NAND flash interface on NAND controller */
+ if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
+ printf("%s: nand flash init failed\n", __func__);
+ goto free;
+ }
+
+ /* first scan to find the device and get the page size */
+ if (nand_scan_ident(mtd, 1, NULL)) {
+ printf("%s: nand_scan_ident failed\n", __func__);
+ goto fail;
+ }
+
+ /* Send the command for reading device ID */
+ nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+ /* Read manufacturer and device IDs */
+ maf_id = nand_chip->read_byte(mtd);
+ dev_id = nand_chip->read_byte(mtd);
+
+ if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
+ (dev_id == 0xa1) || (dev_id == 0xb1) ||
+ (dev_id == 0xaa) || (dev_id == 0xba) ||
+ (dev_id == 0xda) || (dev_id == 0xca) ||
+ (dev_id == 0xac) || (dev_id == 0xbc) ||
+ (dev_id == 0xdc) || (dev_id == 0xcc) ||
+ (dev_id == 0xa3) || (dev_id == 0xb3) ||
+ (dev_id == 0xd3) || (dev_id == 0xc3))) {
+ nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
+ ONDIE_ECC_FEATURE_ADDR, -1);
+
+ for (i = 0; i < 4; i++)
+ writeb(set_feature[i], nand_chip->IO_ADDR_W);
+
+ /* wait for 1us after writing data with SET_FEATURES command */
+ ndelay(1000);
+
+ nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
+ ONDIE_ECC_FEATURE_ADDR, -1);
+ nand_chip->read_buf(mtd, get_feature, 4);
+
+ if (get_feature[0] & 0x08) {
+ debug("%s: OnDie ECC flash\n", __func__);
+ ondie_ecc_enabled = 1;
+ } else {
+ printf("%s: Unable to detect OnDie ECC\n", __func__);
+ }
+ }
+
+ if (ondie_ecc_enabled) {
+ /* bypass the controller ECC block */
+ ecc_cfg = readl(&zynq_nand_smc_base->emcr);
+ ecc_cfg &= ~0xc;
+ writel(ecc_cfg, &zynq_nand_smc_base->emcr);
+
+ /* The software ECC routines won't work
+ * with the SMC controller
+ */
+ nand_chip->ecc.mode = NAND_ECC_HW;
+ nand_chip->ecc.strength = 1;
+ nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
+ nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
+ nand_chip->ecc.write_page = zynq_nand_write_page_raw;
+ nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
+ nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
+ nand_chip->ecc.read_oob = zynq_nand_read_oob;
+ nand_chip->ecc.write_oob = zynq_nand_write_oob;
+ nand_chip->ecc.size = mtd->writesize;
+ nand_chip->ecc.bytes = 0;
+
+ /* NAND with on-die ECC supports subpage reads */
+ nand_chip->options |= NAND_SUBPAGE_READ;
+
+ /* On-Die ECC spare bytes offset 8 is used for ECC codes */
+ if (ondie_ecc_enabled) {
+ nand_chip->ecc.layout = &ondie_nand_oob_64;
+ /* Use the BBT pattern descriptors */
+ nand_chip->bbt_td = &bbt_main_descr;
+ nand_chip->bbt_md = &bbt_mirror_descr;
+ }
+ } else {
+ /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
+ nand_chip->ecc.mode = NAND_ECC_HW;
+ nand_chip->ecc.strength = 1;
+ nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
+ nand_chip->ecc.bytes = 3;
+ nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
+ nand_chip->ecc.correct = zynq_nand_correct_data;
+ nand_chip->ecc.hwctl = NULL;
+ nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
+ nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
+ nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
+ nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
+ nand_chip->ecc.read_oob = zynq_nand_read_oob;
+ nand_chip->ecc.write_oob = zynq_nand_write_oob;
+
+ switch (mtd->writesize) {
+ case 512:
+ ecc_page_size = 0x1;
+ /* Set the ECC memory config register */
+ writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
+ &zynq_nand_smc_base->emcr);
+ break;
+ case 1024:
+ ecc_page_size = 0x2;
+ /* Set the ECC memory config register */
+ writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
+ &zynq_nand_smc_base->emcr);
+ break;
+ case 2048:
+ ecc_page_size = 0x3;
+ /* Set the ECC memory config register */
+ writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
+ &zynq_nand_smc_base->emcr);
+ break;
+ default:
+ /* The software ECC routines won't work with
+ * the SMC controller
+ */
+ nand_chip->ecc.mode = NAND_ECC_HW;
+ nand_chip->ecc.calculate = nand_calculate_ecc;
+ nand_chip->ecc.correct = nand_correct_data;
+ nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
+ /* nand_chip->ecc.read_subpage = nand_read_subpage; */
+ nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
+ nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
+ nand_chip->ecc.write_page_raw =
+ zynq_nand_write_page_raw;
+ nand_chip->ecc.read_oob = zynq_nand_read_oob;
+ nand_chip->ecc.write_oob = zynq_nand_write_oob;
+ nand_chip->ecc.size = 256;
+ nand_chip->ecc.bytes = 3;
+ break;
+ }
+
+ if (mtd->oobsize == 16)
+ nand_chip->ecc.layout = &nand_oob_16;
+ else if (mtd->oobsize == 64)
+ nand_chip->ecc.layout = &nand_oob_64;
+ else
+ ;
+ }
+
+ /* second phase scan */
+ if (nand_scan_tail(mtd)) {
+ printf("%s: nand_scan_tailfailed\n", __func__);
+ goto fail;
+ }
+
+ if (nand_register(devnum, mtd))
+ goto fail;
+
+ return 0;
+fail:
+free:
+ kfree(xnand);
+ return err;
+}
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+void board_nand_init(void)
+{
+ struct nand_chip *nand = &nand_chip[0];
+
+ if (zynq_nand_init(nand, 0))
+ puts("ZYNQ NAND init failed\n");
+}
SF_DUAL_PARALLEL_FLASH = BIT(1),
};
- #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
+/* Enum list - Full read commands */
+enum spi_read_cmds {
+ ARRAY_SLOW = BIT(0),
+ ARRAY_FAST = BIT(1),
+ DUAL_OUTPUT_FAST = BIT(2),
+ QUAD_OUTPUT_FAST = BIT(3),
+ DUAL_IO_FAST = BIT(4),
+ QUAD_IO_FAST = BIT(5),
+};
+
+/* Normal - Extended - Full command set */
+#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
+#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
- #define SST_WR (SST_BP | SST_WP)
-
+
+/* sf param flags */
+enum {
+#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
+ SECT_4K = 0,
+#else
+ SECT_4K = BIT(0),
+#endif
+ SECT_32K = BIT(1),
+ E_FSR = BIT(2),
+ SST_WP = BIT(3),
+ WR_QPP = BIT(4),
+ SST_BP = BIT(5),
+ SST_LOCKBP = BIT(6),
+};
+
enum spi_nor_option_flags {
SNOR_F_SST_WR = BIT(0),
SNOR_F_USE_FSR = BIT(1),
u16 ext_jedec;
u32 sector_size;
u32 nr_sectors;
-
+ u8 e_rd_cmd;
u16 flags;
+ #define SECT_4K BIT(0)
+ #define E_FSR BIT(1)
+ #define SST_WR BIT(2)
+ #define WR_QPP BIT(3)
+ #define RD_QUAD BIT(4)
+ #define RD_DUAL BIT(5)
+ #define RD_QUADIO BIT(6)
+ #define RD_DUALIO BIT(7)
+ #define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO)
};
extern const struct spi_flash_params spi_flash_params_table[];
/* SPI/QSPI flash device params structure */
const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K},
- {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
- {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
- {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K},
- {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
- {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
- {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"AT25DF321A", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
- {"AT25DF321", 0x1f4700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
- {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K},
+ {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K},
+ {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K},
+ {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K},
+ {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K},
+ {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K},
+ {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K},
+ {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K},
+ {"AT25DF321A", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K},
+ {"AT25DF321", 0x1f4700, 0x0, 64 * 1024, 64, SECT_4K},
+ {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
- {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0},
- {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0},
+ {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0},
+ {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K},
+ {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0},
+ {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
+ {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K},
+ {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
- {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_NORM, 0},
- {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, RD_NORM, 0},
+ {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, 0},
+ {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, 0},
+ {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, 0},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0},
- {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0},
- {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0},
- {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0},
- {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0},
- {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
- {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
- {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0},
+ {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0},
+ {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0},
+ {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0},
+ {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0},
+ {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0},
+ {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP},
+ {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP},
+ {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP},
+ {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
- {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0},
- {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0},
- {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0},
- {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0},
- {"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, 0},
- {"S25FL164K", 0x014017, 0x0140, 64 * 1024, 128, 0},
- {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP},
- {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP},
- {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP},
- {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP},
- {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP},
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP},
- {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP},
- {"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP},
- {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP},
- {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP},
+ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0},
+ {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0},
+ {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0},
+ {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0},
+ {"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, RD_NORM, 0},
+ {"S25FL132K", 0x014016, 0x0140, 64 * 1024, 128, RD_FULL, 0},
+ {"S25FL164K", 0x014017, 0x0140, 64 * 1024, 256, RD_FULL, 0},
+ {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
+ {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
+ {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP},
+ {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP},
+ {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
+ {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
+ {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
- {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0},
- {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0},
- {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0},
- {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0},
- {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0},
- {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0},
- {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL},
- {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0},
- {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0},
- {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0},
- {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, SECT_4K},
- {"N25Q016A", 0x20bb15, 0x0, 64 * 1024, 32, SECT_4K},
- {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K},
- {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K},
- {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K},
- {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K},
- {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP},
- {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP},
- {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K},
- {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K},
- {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K},
- {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K},
- {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K},
- {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K},
+ {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0},
+ {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0},
+ {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0},
+ {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0},
+ {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0},
+ {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0},
+ {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0},
+ {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0},
+ {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0},
+ {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0},
+ {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
+ {"N25Q016A", 0x20bb15, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
+ {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
+ {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
+ {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+#ifdef CONFIG_ARCH_ZYNQMP
+ {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR},
+#else
+ {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+#endif
+ {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"MT25QL02G", 0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+ {"MT25QU02G", 0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL, WR_QPP | E_FSR | SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */
- {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR},
- {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR},
- {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR},
- {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR},
- {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K},
- {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR},
- {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR},
- {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR},
- {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR},
- {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, SECT_4K},
- {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR},
+ {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
+ {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
+ {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR},
+ {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR},
+ {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
+ {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF016B", 0xbf2651, 0x0, 4 * 1024, 512, RD_NORM, SST_LOCKBP | SECT_4K},
+ {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
+ {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
- {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0},
- {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0},
- {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0},
- {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
- {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
- {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
- {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
- {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
- {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0},
+ {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0},
+ {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0},
+ {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K},
+ {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K},
+ {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K},
+ {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K},
+ {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K},
+ {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_ISSI
+ {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_EXTN | QUAD_IO_FAST, WR_QPP},
+ {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_EXTN | QUAD_IO_FAST, WR_QPP},
+ {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, RD_EXTN | QUAD_IO_FAST, WR_QPP},
#endif
{}, /* Empty entry to terminate the list */
/*
#include <asm/system.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
- #include <asm-generic/errno.h>
+ #include <linux/errno.h>
+#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
"setenv stdin nc\0" \
"serial=setenv stdout serial;"\
"setenv stdin serial\0"
-
+#endif
+
#define CONFIG_CMDLINE_EDITING
- #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
/* Enable flat device tree support */
#define CONFIG_LMB 1
#define __CONFIG_ZYNQMP_EP_H
#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
-#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
+#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
#define CONFIG_ZYNQ_EEPROM
- #define CONFIG_AHCI
#define CONFIG_SATA_CEVA
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
ZYNQMP_USB1_XHCI_BASEADDR}
--- /dev/null
- #undef CONFIG_FPGA_ZYNQMPPL
- #undef CONFIG_FPGA_XILINX
- #undef CONFIG_FPGA
+/*
+ * Configuration for Xilinx ZynqMP Flash utility
+ *
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ *
+ * Based on Configuration for Versatile Express
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_MINI_H
+#define __CONFIG_ZYNQMP_MINI_H
+
+#define CONFIG_SYS_NO_FLASH
+#define _CONFIG_CMD_DEFAULT_H
+/* #define CONFIG_SYS_DCACHE_OFF */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_FIT_DISABLE_SHA256
+
+#include <configs/xilinx_zynqmp.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_CMD_BOOTZ
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_SYS_HUSH_PARSER
+#undef CONFIG_SYS_PROMPT_HUSH_PS2
+#undef CONFIG_BOOTDELAY
+#undef CONFIG_PREBOOT
+#undef CONFIG_SYS_MALLOC_LEN
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#undef CONFIG_CMD_SPL
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_EXT4
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FS_GENERIC
+#undef CONFIG_CMD_MEMORY
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_CMD_ELF
+#undef CONFIG_MP
+#undef CONFIG_SYS_MEMTEST_START
+#undef CONFIG_SYS_MEMTEST_END
+#undef CONFIG_SYS_INIT_SP_ADDR
+#undef CONFIG_SYS_LONGHELP
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_SF_TEST
+#undef CONFIG_CMD_GPIO
+#undef CONFIG_CMD_SPI
+#undef CONFIG_FIT_VERBOSE
+#undef CONFIG_ZYNQ_SERIAL
+#undef CONFIG_CMD_MII
+
+/* BOOTP options */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+#undef CONFIG_BOOTP_MAY_FAIL
+#undef CONFIG_BOOTP_PXE
+#undef CONFIG_CMD_BOOTI
+#undef CONFIG_CMD_UNZIP
+
+/* PXE */
+#undef CONFIG_CMD_PXE
+#undef CONFIG_MENU
+
+/* Define needed configs */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_BOOTDELAY -1 /* -1 to Disable autoboot */
+
+#undef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS 1
+
+#if defined(CONFIG_MINI_QSPI)
+# define CONFIG_SYS_SDRAM_SIZE (256 * 1024)
+# define CONFIG_SYS_SDRAM_BASE 0xFFFC0000
+# define CONFIG_ENV_SIZE 1400
+# define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x20000)
+# define CONFIG_SYS_MALLOC_LEN 0x2000
+
+#elif defined(CONFIG_MINI_NAND)
+# define CONFIG_SYS_SDRAM_SIZE 0x1000000
+# define CONFIG_SYS_SDRAM_BASE 0
+# define CONFIG_ENV_SIZE 0x10000
+# define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000)
+# define CONFIG_SYS_MALLOC_LEN 0x800000
+
+#elif defined(CONFIG_MINI_EMMC)
+# define CONFIG_ENV_SIZE 0x10000
+# define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+# define CONFIG_SYS_MALLOC_LEN 0x800000
+# define CONFIG_DOS_PARTITION
+# define CONFIG_SYS_LONGHELP
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_FS_GENERIC
+#endif
+
+#endif /* __CONFIG_ZYNQMP_MINI_H */
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds"
+/* FPGA support */
+#define CONFIG_SPL_FPGA_SUPPORT
+#define CONFIG_SPL_FPGA_LOAD_ADDR 0x1000000
+/* #define CONFIG_SPL_FPGA_BIT */
+#ifdef CONFIG_SPL_FPGA_BIT
+# define CONFIG_SPL_FPGA_LOAD_ARGS_NAME "download.bit"
+#else
+# define CONFIG_SPL_FPGA_LOAD_ARGS_NAME "fpga.bin"
+#endif
+
/* MMC support */
#ifdef CONFIG_ZYNQ_SDHCI
- #define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
CONFIG_SYS_SPI_ARGS_SIZE)
#endif
+#define CONFIG_SPL_RAM_DEVICE
+
+#ifdef DEBUG
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_ETH_DEVICE "Gem.e000b000"
+#endif
+
/* for booting directly linux */
- #define CONFIG_SPL_OS_BOOT
/* SP location before relocation, must use scratch RAM */
#define CONFIG_SPL_TEXT_BASE 0x0
* bus (bus->seq) so does not need to be stored
* @cs: ID of the chip select connected to the slave.
* @mode: SPI mode to use for this slave (see SPI mode flags)
- * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
* @wordlen: Size of SPI word in number of bits
+ * @op_mode_rx: SPI RX operation mode.
+ * @op_mode_tx: SPI TX operation mode.
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes.
* @memory_map: Address of read-only SPI flash access.
unsigned int cs;
#endif
uint mode;
- u8 mode_rx;
unsigned int wordlen;
+ u8 op_mode_rx;
+ u8 op_mode_tx;
unsigned int max_write_size;
void *memory_map;
u8 option;
libs-$(CONFIG_SPL_DFU_SUPPORT) += drivers/usb/dwc3/
libs-y += dts/
libs-y += fs/
- libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
+libs-$(CONFIG_SPL_FPGA_SUPPORT) += drivers/fpga/
libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
libs-$(CONFIG_SPL_NET_SUPPORT) += net/
"addr": 0x10000000,
"size": 5058624,
"crc32": "c2244b26",
+ "timeout": 50000,
}
+
+ # Details regarding a file that may be read from a NFS server. This variable
+ # may be omitted or set to None if NFS testing is not possible or desired.
+ env__net_nfs_readable_file = {
+ "fn": "ubtest-readable.bin",
+ "addr": 0x10000000,
+ "size": 5058624,
+ "crc32": "c2244b26",
+ }
"""
net_set_up = False
projects / thirdparty / u-boot.git / commitdiff
