drm/i915/ltphy: Add LT Phy Programming recipe tables

Add the LT Phy programming recipe tables for eDP, DP & HDMI and a
function to use the correct table.

Bspec: 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-9-suraj.kandpal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index f969c5399a511d093eb8d589c5ea96f758cd423b..8c3ef5867a12d0b2c9df5f2140b0519d83e16a8c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -17,6 +17,7 @@
 #include "intel_display_types.h"
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"
+#include "intel_lt_phy.h"
 #include "intel_lvds.h"
 #include "intel_lvds_regs.h"
 #include "intel_panel.h"
@@ -1232,6 +1233,26 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
        return 0;
 }
 
+static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
+                                     struct intel_crtc *crtc)
+{
+       struct intel_crtc_state *crtc_state =
+               intel_atomic_get_new_crtc_state(state, crtc);
+       struct intel_encoder *encoder =
+               intel_get_crtc_new_encoder(state, crtc_state);
+       int ret;
+
+       ret = intel_lt_phy_pll_calc_state(crtc_state, encoder);
+       if (ret)
+               return ret;
+
+       /* TODO: Do the readback via intel_compute_shared_dplls() */
+
+       crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
+       return 0;
+}
+
 static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
 {
        struct intel_display *display = to_intel_display(crtc_state);
@@ -1691,6 +1712,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
        return 0;
 }
 
+static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
+       .crtc_compute_clock = xe3plpd_crtc_compute_clock,
+};
+
 static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
        .crtc_compute_clock = mtl_crtc_compute_clock,
 };
@@ -1789,7 +1814,9 @@ int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
 void
 intel_dpll_init_clock_hook(struct intel_display *display)
 {
-       if (DISPLAY_VER(display) >= 14)
+       if (HAS_LT_PHY(display))
+               display->funcs.dpll = &xe3plpd_dpll_funcs;
+       else if (DISPLAY_VER(display) >= 14)
                display->funcs.dpll = &mtl_dpll_funcs;
        else if (display->platform.dg2)
                display->funcs.dpll = &dg2_dpll_funcs;

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f131bdd1c975de2f126e88d0fdabf73f9e7d9a87..6183da90b28d317212148707de89f50f9e581b6e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -267,6 +267,16 @@ struct intel_cx0pll_state {
        bool tbt_mode;
 };
 
+struct intel_lt_phy_pll_state {
+       u32 clock; /* in kHz */
+       u8 addr_msb[13];
+       u8 addr_lsb[13];
+       u8 data[13][4];
+       u8 config[3];
+       bool ssc_enabled;
+       bool tbt_mode;
+};
+
 struct intel_dpll_hw_state {
        union {
                struct i9xx_dpll_hw_state i9xx;
@@ -276,6 +286,7 @@ struct intel_dpll_hw_state {
                struct icl_dpll_hw_state icl;
                struct intel_mpllb_state mpllb;
                struct intel_cx0pll_state cx0pll;
+               struct intel_lt_phy_pll_state ltpll;
        };
 };
 

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 768b14a9914a709f34c0dbfcbbbf5edfaf57581c..22686da809d0db3af1f1574fe72c8a375ab2f8a9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -12,6 +12,7 @@
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
+#include "intel_dpll_mgr.h"
 #include "intel_hdmi.h"
 #include "intel_lt_phy.h"
 #include "intel_lt_phy_regs.h"
@@ -24,6 +25,957 @@
                                         INTEL_LT_PHY_LANE0)
 #define MODE_DP                                3
 
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
+       .clock = 162000,
+       .config = {
+               0x83,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x5,  0xa,  0x2a, 0x20 },
+               { 0x80, 0x0,  0x0,  0x0  },
+               { 0x4,  0x4,  0x82, 0x28 },
+               { 0xfa, 0x16, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x5,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x4b, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x5b, 0xe0, 0x0a },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = {
+       .clock = 270000,
+       .config = {
+               0x8b,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x3,  0xca, 0x34, 0xa0 },
+               { 0xe0, 0x0,  0x0,  0x0  },
+               { 0x5,  0x4,  0x81, 0xad },
+               { 0xfa, 0x11, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x7,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x43, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x5b, 0xe0, 0x0d },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr2 = {
+       .clock = 540000,
+       .config = {
+               0x93,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x1,  0x4d, 0x34, 0xa0 },
+               { 0xe0, 0x0,  0x0,  0x0  },
+               { 0xa,  0x4,  0x81, 0xda },
+               { 0xfa, 0x11, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x7,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x43, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x5b, 0xe0, 0x0d },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr3 = {
+       .clock = 810000,
+       .config = {
+               0x9b,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x1,  0x4a, 0x34, 0xa0 },
+               { 0xe0, 0x0,  0x0,  0x0  },
+               { 0x5,  0x4,  0x80, 0xa8 },
+               { 0xfa, 0x11, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x7,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x43, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x5b, 0xe0, 0x0d },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr10 = {
+       .clock = 1000000,
+       .config = {
+               0x43,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x85,
+               0x85,
+               0x85,
+               0x85,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x1,  0xa,  0x20, 0x80 },
+               { 0x6a, 0xaa, 0xaa, 0xab },
+               { 0x0,  0x3,  0x4,  0x94 },
+               { 0xfa, 0x1c, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x4,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x45, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x14, 0x2a, 0x14 },
+               { 0x0,  0x5b, 0xe0, 0x8  },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr13_5 = {
+       .clock = 1350000,
+       .config = {
+               0xcb,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x2,  0x9,  0x2b, 0xe0 },
+               { 0x90, 0x0,  0x0,  0x0  },
+               { 0x8,  0x4,  0x80, 0xe0 },
+               { 0xfa, 0x15, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x6,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x49, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x57, 0xe0, 0x0c },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = {
+       .clock = 2000000,
+       .config = {
+               0x53,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x85,
+               0x85,
+               0x85,
+               0x85,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+               0x86,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x1,  0xa,  0x20, 0x80 },
+               { 0x6a, 0xaa, 0xaa, 0xab },
+               { 0x0,  0x3,  0x4,  0x94 },
+               { 0xfa, 0x1c, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x4,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x45, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x14, 0x2a, 0x14 },
+               { 0x0,  0x5b, 0xe0, 0x8  },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state * const xe3plpd_lt_dp_tables[] = {
+       &xe3plpd_lt_dp_rbr,
+       &xe3plpd_lt_dp_hbr1,
+       &xe3plpd_lt_dp_hbr2,
+       &xe3plpd_lt_dp_hbr3,
+       &xe3plpd_lt_dp_uhbr10,
+       &xe3plpd_lt_dp_uhbr13_5,
+       &xe3plpd_lt_dp_uhbr20,
+       NULL,
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
+       .clock = 216000,
+       .config = {
+               0xa3,
+               0x2d,
+               0x1,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x3,  0xca, 0x2a, 0x20 },
+               { 0x80, 0x0,  0x0,  0x0  },
+               { 0x6,  0x4,  0x81, 0xbc },
+               { 0xfa, 0x16, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x5,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x4b, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x5b, 0xe0, 0x0a },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_43 = {
+       .clock = 243000,
+       .config = {
+               0xab,
+               0x2d,
+               0x1,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x3,  0xca, 0x2f, 0x60 },
+               { 0xb0, 0x0,  0x0,  0x0  },
+               { 0x6,  0x4,  0x81, 0xbc },
+               { 0xfa, 0x13, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x6,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x47, 0x48, 0x0,  0x0  },
+               { 0x0,  0x0,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x5b, 0xe0, 0x0c },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_3_24 = {
+       .clock = 324000,
+       .config = {
+               0xb3,
+               0x2d,
+               0x1,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x2,  0x8a, 0x2a, 0x20 },
+               { 0x80, 0x0,  0x0,  0x0  },
+               { 0x6,  0x4,  0x81, 0x28 },
+               { 0xfa, 0x16, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x5,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x4b, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x5b, 0xe0, 0x0a },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_4_32 = {
+       .clock = 432000,
+       .config = {
+               0xbb,
+               0x2d,
+               0x1,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x1,  0x4d, 0x2a, 0x20 },
+               { 0x80, 0x0,  0x0,  0x0  },
+               { 0xc,  0x4,  0x81, 0xbc },
+               { 0xfa, 0x16, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x5,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x4b, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x5b, 0xe0, 0x0a },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = {
+       .clock = 675000,
+       .config = {
+               0xdb,
+               0x2d,
+               0x1,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x1,  0x4a, 0x2b, 0xe0 },
+               { 0x90, 0x0,  0x0,  0x0  },
+               { 0x6,  0x4,  0x80, 0xa8 },
+               { 0xfa, 0x15, 0x83, 0x11 },
+               { 0x80, 0x0f, 0xf9, 0x53 },
+               { 0x84, 0x26, 0x6,  0x4  },
+               { 0x0,  0xe0, 0x1,  0x0  },
+               { 0x49, 0x48, 0x0,  0x0  },
+               { 0x27, 0x8,  0x0,  0x0  },
+               { 0x5a, 0x13, 0x29, 0x13 },
+               { 0x0,  0x57, 0xe0, 0x0c },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state * const xe3plpd_lt_edp_tables[] = {
+       &xe3plpd_lt_dp_rbr,
+       &xe3plpd_lt_edp_2_16,
+       &xe3plpd_lt_edp_2_43,
+       &xe3plpd_lt_dp_hbr1,
+       &xe3plpd_lt_edp_3_24,
+       &xe3plpd_lt_edp_4_32,
+       &xe3plpd_lt_dp_hbr2,
+       &xe3plpd_lt_edp_6_75,
+       &xe3plpd_lt_dp_hbr3,
+       NULL,
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
+       .clock = 25200,
+       .config = {
+               0x84,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x0c, 0x15, 0x27, 0x60 },
+               { 0x0,  0x0,  0x0,  0x0  },
+               { 0x8,  0x4,  0x98, 0x28 },
+               { 0x42, 0x0,  0x84, 0x10 },
+               { 0x80, 0x0f, 0xd9, 0xb5 },
+               { 0x86, 0x0,  0x0,  0x0  },
+               { 0x1,  0xa0, 0x1,  0x0  },
+               { 0x4b, 0x0,  0x0,  0x0  },
+               { 0x28, 0x0,  0x0,  0x0  },
+               { 0x0,  0x14, 0x2a, 0x14 },
+               { 0x0,  0x0,  0x0,  0x0  },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_272 = {
+       .clock = 27200,
+       .config = {
+               0x84,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x0b, 0x15, 0x26, 0xa0 },
+               { 0x60, 0x0,  0x0,  0x0  },
+               { 0x8,  0x4,  0x96, 0x28 },
+               { 0xfa, 0x0c, 0x84, 0x11 },
+               { 0x80, 0x0f, 0xd9, 0x53 },
+               { 0x86, 0x0,  0x0,  0x0  },
+               { 0x1,  0xa0, 0x1,  0x0  },
+               { 0x4b, 0x0,  0x0,  0x0  },
+               { 0x28, 0x0,  0x0,  0x0  },
+               { 0x0,  0x14, 0x2a, 0x14 },
+               { 0x0,  0x0,  0x0,  0x0  },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
+       .clock = 74250,
+       .config = {
+               0x84,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x4,  0x15, 0x26, 0xa0 },
+               { 0x60, 0x0,  0x0,  0x0  },
+               { 0x8,  0x4,  0x88, 0x28 },
+               { 0xfa, 0x0c, 0x84, 0x11 },
+               { 0x80, 0x0f, 0xd9, 0x53 },
+               { 0x86, 0x0,  0x0,  0x0  },
+               { 0x1,  0xa0, 0x1,  0x0  },
+               { 0x4b, 0x0,  0x0,  0x0  },
+               { 0x28, 0x0,  0x0,  0x0  },
+               { 0x0,  0x14, 0x2a, 0x14 },
+               { 0x0,  0x0,  0x0,  0x0  },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_1p485 = {
+       .clock = 148500,
+       .config = {
+               0x84,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x2,  0x15, 0x26, 0xa0 },
+               { 0x60, 0x0,  0x0,  0x0  },
+               { 0x8,  0x4,  0x84, 0x28 },
+               { 0xfa, 0x0c, 0x84, 0x11 },
+               { 0x80, 0x0f, 0xd9, 0x53 },
+               { 0x86, 0x0,  0x0,  0x0  },
+               { 0x1,  0xa0, 0x1,  0x0  },
+               { 0x4b, 0x0,  0x0,  0x0  },
+               { 0x28, 0x0,  0x0,  0x0  },
+               { 0x0,  0x14, 0x2a, 0x14 },
+               { 0x0,  0x0,  0x0,  0x0  },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
+       .clock = 594000,
+       .config = {
+               0x84,
+               0x2d,
+               0x0,
+       },
+       .addr_msb = {
+               0x87,
+               0x87,
+               0x87,
+               0x87,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+               0x88,
+       },
+       .addr_lsb = {
+               0x10,
+               0x0c,
+               0x14,
+               0xe4,
+               0x0c,
+               0x10,
+               0x14,
+               0x18,
+               0x48,
+               0x40,
+               0x4c,
+               0x24,
+               0x44,
+       },
+       .data = {
+               { 0x0,  0x4c, 0x2,  0x0  },
+               { 0x0,  0x95, 0x26, 0xa0 },
+               { 0x60, 0x0,  0x0,  0x0  },
+               { 0x8,  0x4,  0x81, 0x28 },
+               { 0xfa, 0x0c, 0x84, 0x11 },
+               { 0x80, 0x0f, 0xd9, 0x53 },
+               { 0x86, 0x0,  0x0,  0x0  },
+               { 0x1,  0xa0, 0x1,  0x0  },
+               { 0x4b, 0x0,  0x0,  0x0  },
+               { 0x28, 0x0,  0x0,  0x0  },
+               { 0x0,  0x14, 0x2a, 0x14 },
+               { 0x0,  0x0,  0x0,  0x0  },
+               { 0x0,  0x0,  0x0,  0x0  },
+       },
+};
+
+static const struct intel_lt_phy_pll_state * const xe3plpd_lt_hdmi_tables[] = {
+       &xe3plpd_lt_hdmi_252,
+       &xe3plpd_lt_hdmi_272,
+       &xe3plpd_lt_hdmi_742p5,
+       &xe3plpd_lt_hdmi_1p485,
+       &xe3plpd_lt_hdmi_5p94,
+       NULL,
+};
+
 static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
 {
        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
@@ -236,6 +1188,46 @@ static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, intel_wa
        intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
 }
 
+static const struct intel_lt_phy_pll_state * const *
+intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
+                           struct intel_encoder *encoder)
+{
+       if (intel_crtc_has_dp_encoder(crtc_state)) {
+               if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+                       return xe3plpd_lt_edp_tables;
+
+               return xe3plpd_lt_dp_tables;
+       } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+               return xe3plpd_lt_hdmi_tables;
+       }
+
+       MISSING_CASE(encoder->type);
+       return NULL;
+}
+
+int
+intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
+                           struct intel_encoder *encoder)
+{
+       const struct intel_lt_phy_pll_state * const *tables;
+       int i;
+
+       tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
+       if (!tables)
+               return -EINVAL;
+
+       for (i = 0; tables[i]; i++) {
+               if (crtc_state->port_clock == tables[i]->clock) {
+                       crtc_state->dpll_hw_state.ltpll = *tables[i];
+                       return 0;
+               }
+       }
+
+       /* TODO: Add a function to compute the data for HDMI TMDS*/
+
+       return -EINVAL;
+}
+
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
                             const struct intel_crtc_state *crtc_state)
 {

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index bd3ff3007e1d53b4b255d4024e97daffb4fcb02c..3f255c9b0f96391f46da4d08de189901fc79bdaf 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -13,5 +13,10 @@ struct intel_crtc_state;
 
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
                             const struct intel_crtc_state *crtc_state);
+int
+intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
+                           struct intel_encoder *encoder);
+
+#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
 
 #endif /* __INTEL_LT_PHY_H__ */