--- /dev/null
+From 8c42a5c02bec6c7eccf08957be3c6c8fccf9790b Mon Sep 17 00:00:00 2001
+From: Vineet Gupta <vgupta@synopsys.com>
+Date: Thu, 22 Oct 2020 03:16:22 -0700
+Subject: ARC: perf: redo the pct irq missing in device-tree handling
+
+From: Vineet Gupta <vgupta@synopsys.com>
+
+commit 8c42a5c02bec6c7eccf08957be3c6c8fccf9790b upstream.
+
+commit feb92d7d3813456c11dce21 "(ARC: perf: don't bail setup if pct irq
+missing in device-tree)" introduced a silly brown-paper bag bug:
+The assignment and comparison in an if statement were not bracketed
+correctly leaving the order of evaluation undefined.
+
+|
+| if (has_interrupts && (irq = platform_get_irq(pdev, 0) >= 0)) {
+| ^^^ ^^^^
+
+And given such a chance, the compiler will bite you hard, fully entitled
+to generating this piece of beauty:
+
+|
+| # if (has_interrupts && (irq = platform_get_irq(pdev, 0) >= 0)) {
+|
+| bl.d @platform_get_irq <-- irq returned in r0
+|
+| setge r2, r0, 0 <-- r2 is bool 1 or 0 if irq >= 0 true/false
+| brlt.d r0, 0, @.L114
+|
+| st_s r2,[sp] <-- irq saved is bool 1 or 0, not actual return val
+| st 1,[r3,160] # arc_pmu.18_29->irq <-- drops bool and assumes 1
+|
+| # return __request_percpu_irq(irq, handler, 0,
+|
+| bl.d @__request_percpu_irq;
+| mov_s r0,1 <-- drops even bool and assumes 1 which fails
+
+With the snafu fixed, everything is as expected.
+
+| bl.d @platform_get_irq <-- returns irq in r0
+|
+| mov_s r2,r0
+| brlt.d r2, 0, @.L112
+|
+| st_s r0,[sp] <-- irq isaved is actual return value above
+| st r0,[r13,160] #arc_pmu.18_27->irq
+|
+| bl.d @__request_percpu_irq <-- r0 unchanged so actual irq returned
+| add r4,r4,r12 #, tmp363, __ptr
+
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arc/kernel/perf_event.c | 29 +++++++++++++++++++----------
+ 1 file changed, 19 insertions(+), 10 deletions(-)
+
+--- a/arch/arc/kernel/perf_event.c
++++ b/arch/arc/kernel/perf_event.c
+@@ -562,7 +562,7 @@ static int arc_pmu_device_probe(struct p
+ {
+ struct arc_reg_pct_build pct_bcr;
+ struct arc_reg_cc_build cc_bcr;
+- int i, has_interrupts, irq;
++ int i, has_interrupts, irq = -1;
+ int counter_size; /* in bits */
+
+ union cc_name {
+@@ -637,18 +637,27 @@ static int arc_pmu_device_probe(struct p
+ .attr_groups = arc_pmu->attr_groups,
+ };
+
+- if (has_interrupts && (irq = platform_get_irq(pdev, 0) >= 0)) {
++ if (has_interrupts) {
++ irq = platform_get_irq(pdev, 0);
++ if (irq >= 0) {
++ int ret;
++
++ arc_pmu->irq = irq;
++
++ /* intc map function ensures irq_set_percpu_devid() called */
++ ret = request_percpu_irq(irq, arc_pmu_intr, "ARC perf counters",
++ this_cpu_ptr(&arc_pmu_cpu));
++
++ if (!ret)
++ on_each_cpu(arc_cpu_pmu_irq_init, &irq, 1);
++ else
++ irq = -1;
++ }
+
+- arc_pmu->irq = irq;
+-
+- /* intc map function ensures irq_set_percpu_devid() called */
+- request_percpu_irq(irq, arc_pmu_intr, "ARC perf counters",
+- this_cpu_ptr(&arc_pmu_cpu));
++ }
+
+- on_each_cpu(arc_cpu_pmu_irq_init, &irq, 1);
+- } else {
++ if (irq == -1)
+ arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
+- }
+
+ /*
+ * perf parser doesn't really like '-' symbol in events name, so let's
--- /dev/null
+From 5dff80bdce9e385af5716ed083f9e33e814484ab Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 14 Oct 2020 13:12:30 -0400
+Subject: drm/amd/display: Avoid MST manager resource leak.
+
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+
+commit 5dff80bdce9e385af5716ed083f9e33e814484ab upstream.
+
+On connector destruction call drm_dp_mst_topology_mgr_destroy
+to release resources allocated in drm_dp_mst_topology_mgr_init.
+Do it only if MST manager was initilized before otherwsie a crash
+is seen on driver unload/device unplug.
+
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4882,6 +4882,13 @@ static void amdgpu_dm_connector_destroy(
+ struct amdgpu_device *adev = connector->dev->dev_private;
+ struct amdgpu_display_manager *dm = &adev->dm;
+
++ /*
++ * Call only if mst_mgr was iniitalized before since it's not done
++ * for all connector types.
++ */
++ if (aconnector->mst_mgr.dev)
++ drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
++
+ #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
+ defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
+
--- /dev/null
+From 651111be24aa4c8b62c10f6fff51d9ad82411249 Mon Sep 17 00:00:00 2001
+From: David Galiffi <David.Galiffi@amd.com>
+Date: Thu, 3 Sep 2020 19:20:36 -0400
+Subject: drm/amd/display: Fix incorrect backlight register offset for DCN
+
+From: David Galiffi <David.Galiffi@amd.com>
+
+commit 651111be24aa4c8b62c10f6fff51d9ad82411249 upstream.
+
+[Why]
+Typo in backlight refactor introduced wrong register offset.
+
+[How]
+SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2).
+
+Signed-off-by: David Galiffi <David.Galiffi@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
+@@ -54,7 +54,7 @@
+ SR(BL_PWM_CNTL2), \
+ SR(BL_PWM_PERIOD_CNTL), \
+ SR(BL_PWM_GRP1_REG_LOCK), \
+- SR(BIOS_SCRATCH_2)
++ NBIO_SR(BIOS_SCRATCH_2)
+
+ #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
--- /dev/null
+From 37b7cb10f07c1174522faafc1d51c6591b1501d4 Mon Sep 17 00:00:00 2001
+From: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Date: Wed, 9 Sep 2020 17:41:53 -0400
+Subject: drm/amd/display: Increase timeout for DP Disable
+
+From: Wesley Chalmers <Wesley.Chalmers@amd.com>
+
+commit 37b7cb10f07c1174522faafc1d51c6591b1501d4 upstream.
+
+[WHY]
+When disabling DP video, the current REG_WAIT timeout
+of 50ms is too low for certain cases with very high
+VSYNC intervals.
+
+[HOW]
+Increase the timeout to 102ms, so that
+refresh rates as low as 10Hz can be handled properly.
+
+Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+@@ -896,10 +896,10 @@ void enc1_stream_encoder_dp_blank(
+ */
+ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
+ /* Larger delay to wait until VBLANK - use max retry of
+- * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode +
++ * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
+ * a little more because we may not trust delay accuracy.
+ */
+- max_retries = DP_BLANK_MAX_RETRY * 250;
++ max_retries = DP_BLANK_MAX_RETRY * 501;
+
+ /* disable DP stream */
+ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
--- /dev/null
+From 207ac684792560acdb9e06f9d707ebf63c84b0e0 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 15 Oct 2020 14:57:46 +0800
+Subject: drm/amdgpu: correct the gpu reset handling for job != NULL case
+
+From: Evan Quan <evan.quan@amd.com>
+
+commit 207ac684792560acdb9e06f9d707ebf63c84b0e0 upstream.
+
+Current code wrongly treat all cases as job == NULL.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-and-tested-by: Jane Jian <Jane.Jian@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -4374,7 +4374,7 @@ int amdgpu_device_gpu_recover(struct amd
+ retry: /* Rest of adevs pre asic reset from XGMI hive. */
+ list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+ r = amdgpu_device_pre_asic_reset(tmp_adev,
+- NULL,
++ (tmp_adev == adev) ? job : NULL,
+ &need_full_reset);
+ /*TODO Should we stop ?*/
+ if (r) {
--- /dev/null
+From c4aa8dff6091cc9536aeb255e544b0b4ba29faf4 Mon Sep 17 00:00:00 2001
+From: Madhav Chauhan <madhav.chauhan@amd.com>
+Date: Fri, 16 Oct 2020 18:03:07 +0530
+Subject: drm/amdgpu: don't map BO in reserved region
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Madhav Chauhan <madhav.chauhan@amd.com>
+
+commit c4aa8dff6091cc9536aeb255e544b0b4ba29faf4 upstream.
+
+2MB area is reserved at top inside VM.
+
+Suggested-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Madhav Chauhan <madhav.chauhan@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+@@ -596,6 +596,7 @@ int amdgpu_gem_va_ioctl(struct drm_devic
+ struct ww_acquire_ctx ticket;
+ struct list_head list, duplicates;
+ uint64_t va_flags;
++ uint64_t vm_size;
+ int r = 0;
+
+ if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
+@@ -616,6 +617,15 @@ int amdgpu_gem_va_ioctl(struct drm_devic
+
+ args->va_address &= AMDGPU_GMC_HOLE_MASK;
+
++ vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
++ vm_size -= AMDGPU_VA_RESERVED_SIZE;
++ if (args->va_address + args->map_size > vm_size) {
++ dev_dbg(&dev->pdev->dev,
++ "va_address 0x%llx is in top reserved area 0x%llx\n",
++ args->va_address + args->map_size, vm_size);
++ return -EINVAL;
++ }
++
+ if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
+ dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
+ args->flags);
--- /dev/null
+From 0d142232d9436acab3578ee995472f58adcbf201 Mon Sep 17 00:00:00 2001
+From: Likun Gao <Likun.Gao@amd.com>
+Date: Thu, 15 Oct 2020 10:48:15 +0800
+Subject: drm/amdgpu: update golden setting for sienna_cichlid
+
+From: Likun Gao <Likun.Gao@amd.com>
+
+commit 0d142232d9436acab3578ee995472f58adcbf201 upstream.
+
+Update golden setting for sienna_cichlid.
+
+Signed-off-by: Likun Gao <Likun.Gao@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 5.9.x
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -3091,6 +3091,7 @@ static const struct soc15_reg_golden gol
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
--- /dev/null
+From 187561dd76531945126b15c9486fec7cfa5f0415 Mon Sep 17 00:00:00 2001
+From: Veerabadhran G <vegopala@amd.com>
+Date: Thu, 8 Oct 2020 22:30:02 +0530
+Subject: drm/amdgpu: vcn and jpeg ring synchronization
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Veerabadhran G <vegopala@amd.com>
+
+commit 187561dd76531945126b15c9486fec7cfa5f0415 upstream.
+
+Synchronize the ring usage for vcn1 and jpeg1 to workaround a hardware bug.
+
+Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 24 ++++++++++++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 28 ++++++++++++++++++++++++----
+ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h | 3 ++-
+ 5 files changed, 51 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -68,6 +68,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_dev
+
+ INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
+ mutex_init(&adev->vcn.vcn_pg_lock);
++ mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
+ atomic_set(&adev->vcn.total_submission_cnt, 0);
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++)
+ atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
+@@ -237,6 +238,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_dev
+ }
+
+ release_firmware(adev->vcn.fw);
++ mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
+ mutex_destroy(&adev->vcn.vcn_pg_lock);
+
+ return 0;
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+@@ -220,6 +220,7 @@ struct amdgpu_vcn {
+ struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];
+ struct amdgpu_vcn_reg internal;
+ struct mutex vcn_pg_lock;
++ struct mutex vcn1_jpeg1_workaround;
+ atomic_t total_submission_cnt;
+
+ unsigned harvest_config;
+--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+@@ -33,6 +33,7 @@
+
+ static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+ static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);
++static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring);
+
+ static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
+ {
+@@ -564,8 +565,8 @@ static const struct amdgpu_ring_funcs jp
+ .insert_start = jpeg_v1_0_decode_ring_insert_start,
+ .insert_end = jpeg_v1_0_decode_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+- .begin_use = vcn_v1_0_ring_begin_use,
+- .end_use = amdgpu_vcn_ring_end_use,
++ .begin_use = jpeg_v1_0_ring_begin_use,
++ .end_use = vcn_v1_0_ring_end_use,
+ .emit_wreg = jpeg_v1_0_decode_ring_emit_wreg,
+ .emit_reg_wait = jpeg_v1_0_decode_ring_emit_reg_wait,
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+@@ -586,3 +587,22 @@ static void jpeg_v1_0_set_irq_funcs(stru
+ {
+ adev->jpeg.inst->irq.funcs = &jpeg_v1_0_irq_funcs;
+ }
++
++static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++ bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
++ int cnt = 0;
++
++ mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
++
++ if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_dec))
++ DRM_ERROR("JPEG dec: vcn dec ring may not be empty\n");
++
++ for (cnt = 0; cnt < adev->vcn.num_enc_rings; cnt++) {
++ if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_enc[cnt]))
++ DRM_ERROR("JPEG dec: vcn enc ring[%d] may not be empty\n", cnt);
++ }
++
++ vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
++}
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+@@ -54,6 +54,7 @@ static int vcn_v1_0_pause_dpg_mode(struc
+ int inst_idx, struct dpg_pause_state *new_state);
+
+ static void vcn_v1_0_idle_work_handler(struct work_struct *work);
++static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
+
+ /**
+ * vcn_v1_0_early_init - set function pointers
+@@ -1804,11 +1805,24 @@ static void vcn_v1_0_idle_work_handler(s
+ }
+ }
+
+-void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
++static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
+ {
+- struct amdgpu_device *adev = ring->adev;
++ struct amdgpu_device *adev = ring->adev;
+ bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
+
++ mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
++
++ if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec))
++ DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
++
++ vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
++
++}
++
++void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
++{
++ struct amdgpu_device *adev = ring->adev;
++
+ if (set_clocks) {
+ amdgpu_gfx_off_ctrl(adev, false);
+ if (adev->pm.dpm_enabled)
+@@ -1844,6 +1858,12 @@ void vcn_v1_0_ring_begin_use(struct amdg
+ }
+ }
+
++void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
++{
++ schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
++ mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
++}
++
+ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
+ .name = "vcn_v1_0",
+ .early_init = vcn_v1_0_early_init,
+@@ -1891,7 +1911,7 @@ static const struct amdgpu_ring_funcs vc
+ .insert_end = vcn_v1_0_dec_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = vcn_v1_0_ring_begin_use,
+- .end_use = amdgpu_vcn_ring_end_use,
++ .end_use = vcn_v1_0_ring_end_use,
+ .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
+ .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+@@ -1923,7 +1943,7 @@ static const struct amdgpu_ring_funcs vc
+ .insert_end = vcn_v1_0_enc_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = vcn_v1_0_ring_begin_use,
+- .end_use = amdgpu_vcn_ring_end_use,
++ .end_use = vcn_v1_0_ring_end_use,
+ .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
+ .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
+@@ -24,7 +24,8 @@
+ #ifndef __VCN_V1_0_H__
+ #define __VCN_V1_0_H__
+
+-void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
++void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring);
++void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks);
+
+ extern const struct amdgpu_ip_block_version vcn_v1_0_ip_block;
+
--- /dev/null
+From d56b1980d7efe9ef08469e856fc0703d0cef65e4 Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Sat, 17 Oct 2020 08:38:43 -0500
+Subject: drm/amdkfd: Use same SQ prefetch setting as amdgpu
+
+From: Jay Cornwall <jay.cornwall@amd.com>
+
+commit d56b1980d7efe9ef08469e856fc0703d0cef65e4 upstream.
+
+0 causes instruction fetch stall at cache line boundary under some
+conditions on Navi10. A non-zero prefetch is the preferred default
+in any case.
+
+Fixes soft hang in Luxmark.
+
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
+@@ -58,8 +58,9 @@ static int update_qpd_v10(struct device_
+ /* check if sh_mem_config register already configured */
+ if (qpd->sh_mem_config == 0) {
+ qpd->sh_mem_config =
+- SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
+- SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
++ (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
++ SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
++ (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
+ #if 0
+ /* TODO:
+ * This shouldn't be an issue with Navi10. Verify.
--- /dev/null
+From e50e4f0b85be308a01b830c5fbdffc657e1a6dd0 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzk@kernel.org>
+Date: Sun, 20 Sep 2020 23:12:38 +0200
+Subject: i2c: imx: Fix external abort on interrupt in exit paths
+
+From: Krzysztof Kozlowski <krzk@kernel.org>
+
+commit e50e4f0b85be308a01b830c5fbdffc657e1a6dd0 upstream.
+
+If interrupt comes late, during probe error path or device remove (could
+be triggered with CONFIG_DEBUG_SHIRQ), the interrupt handler
+i2c_imx_isr() will access registers with the clock being disabled. This
+leads to external abort on non-linefetch on Toradex Colibri VF50 module
+(with Vybrid VF5xx):
+
+ Unhandled fault: external abort on non-linefetch (0x1008) at 0x8882d003
+ Internal error: : 1008 [#1] ARM
+ Modules linked in:
+ CPU: 0 PID: 1 Comm: swapper Not tainted 5.7.0 #607
+ Hardware name: Freescale Vybrid VF5xx/VF6xx (Device Tree)
+ (i2c_imx_isr) from [<8017009c>] (free_irq+0x25c/0x3b0)
+ (free_irq) from [<805844ec>] (release_nodes+0x178/0x284)
+ (release_nodes) from [<80580030>] (really_probe+0x10c/0x348)
+ (really_probe) from [<80580380>] (driver_probe_device+0x60/0x170)
+ (driver_probe_device) from [<80580630>] (device_driver_attach+0x58/0x60)
+ (device_driver_attach) from [<805806bc>] (__driver_attach+0x84/0xc0)
+ (__driver_attach) from [<8057e228>] (bus_for_each_dev+0x68/0xb4)
+ (bus_for_each_dev) from [<8057f3ec>] (bus_add_driver+0x144/0x1ec)
+ (bus_add_driver) from [<80581320>] (driver_register+0x78/0x110)
+ (driver_register) from [<8010213c>] (do_one_initcall+0xa8/0x2f4)
+ (do_one_initcall) from [<80c0100c>] (kernel_init_freeable+0x178/0x1dc)
+ (kernel_init_freeable) from [<80807048>] (kernel_init+0x8/0x110)
+ (kernel_init) from [<80100114>] (ret_from_fork+0x14/0x20)
+
+Additionally, the i2c_imx_isr() could wake up the wait queue
+(imx_i2c_struct->queue) before its initialization happens.
+
+The resource-managed framework should not be used for interrupt handling,
+because the resource will be released too late - after disabling clocks.
+The interrupt handler is not prepared for such case.
+
+Fixes: 1c4b6c3bcf30 ("i2c: imx: implement bus recovery")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
+Acked-by: Oleksij Rempel <o.rempel@pengutronix.de>
+Signed-off-by: Wolfram Sang <wsa@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/i2c/busses/i2c-imx.c | 24 +++++++++++++-----------
+ 1 file changed, 13 insertions(+), 11 deletions(-)
+
+--- a/drivers/i2c/busses/i2c-imx.c
++++ b/drivers/i2c/busses/i2c-imx.c
+@@ -1171,14 +1171,6 @@ static int i2c_imx_probe(struct platform
+ return ret;
+ }
+
+- /* Request IRQ */
+- ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED,
+- pdev->name, i2c_imx);
+- if (ret) {
+- dev_err(&pdev->dev, "can't claim irq %d\n", irq);
+- goto clk_disable;
+- }
+-
+ /* Init queue */
+ init_waitqueue_head(&i2c_imx->queue);
+
+@@ -1197,6 +1189,14 @@ static int i2c_imx_probe(struct platform
+ if (ret < 0)
+ goto rpm_disable;
+
++ /* Request IRQ */
++ ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED,
++ pdev->name, i2c_imx);
++ if (ret) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", irq);
++ goto rpm_disable;
++ }
++
+ /* Set up clock divider */
+ i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
+ ret = of_property_read_u32(pdev->dev.of_node,
+@@ -1239,13 +1239,12 @@ static int i2c_imx_probe(struct platform
+
+ clk_notifier_unregister:
+ clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
++ free_irq(irq, i2c_imx);
+ rpm_disable:
+ pm_runtime_put_noidle(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
+ pm_runtime_dont_use_autosuspend(&pdev->dev);
+-
+-clk_disable:
+ clk_disable_unprepare(i2c_imx->clk);
+ return ret;
+ }
+@@ -1253,7 +1252,7 @@ clk_disable:
+ static int i2c_imx_remove(struct platform_device *pdev)
+ {
+ struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
+- int ret;
++ int irq, ret;
+
+ ret = pm_runtime_get_sync(&pdev->dev);
+ if (ret < 0)
+@@ -1273,6 +1272,9 @@ static int i2c_imx_remove(struct platfor
+ imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
+
+ clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
++ irq = platform_get_irq(pdev, 0);
++ if (irq >= 0)
++ free_irq(irq, i2c_imx);
+ clk_disable_unprepare(i2c_imx->clk);
+
+ pm_runtime_put_noidle(&pdev->dev);
--- /dev/null
+From 7404840d87557c4092bf0272bce5e0354c774bf9 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzk@kernel.org>
+Date: Sat, 17 Oct 2020 16:13:37 -0700
+Subject: ia64: fix build error with !COREDUMP
+
+From: Krzysztof Kozlowski <krzk@kernel.org>
+
+commit 7404840d87557c4092bf0272bce5e0354c774bf9 upstream.
+
+Fix linkage error when CONFIG_BINFMT_ELF is selected but CONFIG_COREDUMP
+is not:
+
+ ia64-linux-ld: arch/ia64/kernel/elfcore.o: in function `elf_core_write_extra_phdrs':
+ elfcore.c:(.text+0x172): undefined reference to `dump_emit'
+ ia64-linux-ld: arch/ia64/kernel/elfcore.o: in function `elf_core_write_extra_data':
+ elfcore.c:(.text+0x2b2): undefined reference to `dump_emit'
+
+Fixes: 1fcccbac89f5 ("elf coredump: replace ELF_CORE_EXTRA_* macros by functions")
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Cc: Tony Luck <tony.luck@intel.com>
+Cc: Fenghua Yu <fenghua.yu@intel.com>
+Cc: <stable@vger.kernel.org>
+Link: https://lkml.kernel.org/r/20200819064146.12529-1-krzk@kernel.org
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/ia64/kernel/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/ia64/kernel/Makefile
++++ b/arch/ia64/kernel/Makefile
+@@ -41,7 +41,7 @@ obj-y += esi_stub.o # must be in kern
+ endif
+ obj-$(CONFIG_INTEL_IOMMU) += pci-dma.o
+
+-obj-$(CONFIG_BINFMT_ELF) += elfcore.o
++obj-$(CONFIG_ELF_CORE) += elfcore.o
+
+ # fp_emulate() expects f2-f5,f16-f31 to contain the user-level state.
+ CFLAGS_traps.o += -mfixed-range=f2-f5,f16-f31
--- /dev/null
+From 6fcd5ddc3b1467b3586972ef785d0d926ae4cdf4 Mon Sep 17 00:00:00 2001
+From: Jiri Olsa <jolsa@kernel.org>
+Date: Mon, 28 Sep 2020 22:11:35 +0200
+Subject: perf python scripting: Fix printable strings in python3 scripts
+
+From: Jiri Olsa <jolsa@kernel.org>
+
+commit 6fcd5ddc3b1467b3586972ef785d0d926ae4cdf4 upstream.
+
+Hagen reported broken strings in python3 tracepoint scripts:
+
+ make PYTHON=python3
+ perf record -e sched:sched_switch -a -- sleep 5
+ perf script --gen-script py
+ perf script -s ./perf-script.py
+
+ [..]
+ sched__sched_switch 7 563231.759525792 0 swapper prev_comm=bytearray(b'swapper/7\x00\x00\x00\x00\x00\x00\x00'), prev_pid=0, prev_prio=120, prev_state=, next_comm=bytearray(b'mutex-thread-co\x00'),
+
+The problem is in the is_printable_array function that does not take the
+zero byte into account and claim such string as not printable, so the
+code will create byte array instead of string.
+
+Committer testing:
+
+After this fix:
+
+sched__sched_switch 3 484522.497072626 1158680 kworker/3:0-eve prev_comm=kworker/3:0, prev_pid=1158680, prev_prio=120, prev_state=I, next_comm=swapper/3, next_pid=0, next_prio=120
+Sample: {addr=0, cpu=3, datasrc=84410401, datasrc_decode=N/A|SNP N/A|TLB N/A|LCK N/A, ip=18446744071841817196, period=1, phys_addr=0, pid=1158680, tid=1158680, time=484522497072626, transaction=0, values=[(0, 0)], weight=0}
+
+sched__sched_switch 4 484522.497085610 1225814 perf prev_comm=perf, prev_pid=1225814, prev_prio=120, prev_state=, next_comm=migration/4, next_pid=30, next_prio=0
+Sample: {addr=0, cpu=4, datasrc=84410401, datasrc_decode=N/A|SNP N/A|TLB N/A|LCK N/A, ip=18446744071841817196, period=1, phys_addr=0, pid=1225814, tid=1225814, time=484522497085610, transaction=0, values=[(0, 0)], weight=0}
+
+Fixes: 249de6e07458 ("perf script python: Fix string vs byte array resolving")
+Signed-off-by: Jiri Olsa <jolsa@kernel.org>
+Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+Tested-by: Hagen Paul Pfeifer <hagen@jauu.net>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Mark Rutland <mark.rutland@arm.com>
+Cc: Michael Petlan <mpetlan@redhat.com>
+Cc: Namhyung Kim <namhyung@kernel.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: stable@vger.kernel.org
+Link: http://lore.kernel.org/lkml/20200928201135.3633850-1-jolsa@kernel.org
+Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ tools/perf/util/print_binary.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/tools/perf/util/print_binary.c
++++ b/tools/perf/util/print_binary.c
+@@ -50,7 +50,7 @@ int is_printable_array(char *p, unsigned
+
+ len--;
+
+- for (i = 0; i < len; i++) {
++ for (i = 0; i < len && p[i]; i++) {
+ if (!isprint(p[i]) && !isspace(p[i]))
+ return 0;
+ }
--- /dev/null
+From 60d804521ec4cd01217a96f33cd1bb29e295333d Mon Sep 17 00:00:00 2001
+From: Kim Phillips <kim.phillips@amd.com>
+Date: Tue, 1 Sep 2020 17:09:41 -0500
+Subject: perf vendor events amd: Add L2 Prefetch events for zen1
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Kim Phillips <kim.phillips@amd.com>
+
+commit 60d804521ec4cd01217a96f33cd1bb29e295333d upstream.
+
+Later revisions of PPRs that post-date the original Family 17h events
+submission patch add these events.
+
+Specifically, they were not in this 2017 revision of the F17h PPR:
+
+Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors Rev 1.14 - April 15, 2017
+
+But e.g., are included in this 2019 version of the PPR:
+
+Processor Programming Reference (PPR) for AMD Family 17h Model 18h, Revision B1 Processors Rev. 3.14 - Sep 26, 2019
+
+Fixes: 98c07a8f74f8 ("perf vendor events amd: perf PMU events for AMD Family 17h")
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
+Signed-off-by: Kim Phillips <kim.phillips@amd.com>
+Reviewed-by: Ian Rogers <irogers@google.com>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Andi Kleen <ak@linux.intel.com>
+Cc: Borislav Petkov <bp@suse.de>
+Cc: Jin Yao <yao.jin@linux.intel.com>
+Cc: Jiri Olsa <jolsa@redhat.com>
+Cc: John Garry <john.garry@huawei.com>
+Cc: Jon Grimm <jon.grimm@amd.com>
+Cc: Kan Liang <kan.liang@linux.intel.com>
+Cc: Mark Rutland <mark.rutland@arm.com>
+Cc: Martin Jambor <mjambor@suse.cz>
+Cc: Martin Liška <mliska@suse.cz>
+Cc: Michael Petlan <mpetlan@redhat.com>
+Cc: Namhyung Kim <namhyung@kernel.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: stable@vger.kernel.org
+Cc: Stephane Eranian <eranian@google.com>
+Cc: Vijay Thakkar <vijaythakkar@me.com>
+Cc: William Cohen <wcohen@redhat.com>
+Cc: Yunfeng Ye <yeyunfeng@huawei.com>
+Link: http://lore.kernel.org/lkml/20200901220944.277505-1-kim.phillips@amd.com
+Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ tools/perf/pmu-events/arch/x86/amdzen1/cache.json | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json
++++ b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json
+@@ -250,6 +250,24 @@
+ "UMask": "0x1"
+ },
+ {
++ "EventName": "l2_pf_hit_l2",
++ "EventCode": "0x70",
++ "BriefDescription": "L2 prefetch hit in L2.",
++ "UMask": "0xff"
++ },
++ {
++ "EventName": "l2_pf_miss_l2_hit_l3",
++ "EventCode": "0x71",
++ "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.",
++ "UMask": "0xff"
++ },
++ {
++ "EventName": "l2_pf_miss_l2_l3",
++ "EventCode": "0x72",
++ "BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.",
++ "UMask": "0xff"
++ },
++ {
+ "EventName": "l3_request_g1.caching_l3_cache_accesses",
+ "EventCode": "0x01",
+ "BriefDescription": "Caching: L3 cache accesses",
--- /dev/null
+From d3b14296da69adb7825022f3224ac6137eb30abf Mon Sep 17 00:00:00 2001
+From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Date: Mon, 14 Sep 2020 17:45:48 +0200
+Subject: rtc: rx8010: don't modify the global rtc ops
+
+From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+
+commit d3b14296da69adb7825022f3224ac6137eb30abf upstream.
+
+The way the driver is implemented is buggy for the (admittedly unlikely)
+use case where there are two RTCs with one having an interrupt configured
+and the second not. This is caused by the fact that we use a global
+rtc_class_ops struct which we modify depending on whether the irq number
+is present or not.
+
+Fix it by using two const ops structs with and without alarm operations.
+While at it: not being able to request a configured interrupt is an error
+so don't ignore it and bail out of probe().
+
+Fixes: ed13d89b08e3 ("rtc: Add Epson RX8010SJ RTC driver")
+Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20200914154601.32245-2-brgl@bgdev.pl
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/rtc/rtc-rx8010.c | 24 +++++++++++++++++-------
+ 1 file changed, 17 insertions(+), 7 deletions(-)
+
+--- a/drivers/rtc/rtc-rx8010.c
++++ b/drivers/rtc/rtc-rx8010.c
+@@ -407,16 +407,26 @@ static int rx8010_ioctl(struct device *d
+ }
+ }
+
+-static struct rtc_class_ops rx8010_rtc_ops = {
++static const struct rtc_class_ops rx8010_rtc_ops_default = {
+ .read_time = rx8010_get_time,
+ .set_time = rx8010_set_time,
+ .ioctl = rx8010_ioctl,
+ };
+
++static const struct rtc_class_ops rx8010_rtc_ops_alarm = {
++ .read_time = rx8010_get_time,
++ .set_time = rx8010_set_time,
++ .ioctl = rx8010_ioctl,
++ .read_alarm = rx8010_read_alarm,
++ .set_alarm = rx8010_set_alarm,
++ .alarm_irq_enable = rx8010_alarm_irq_enable,
++};
++
+ static int rx8010_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+ {
+ struct i2c_adapter *adapter = client->adapter;
++ const struct rtc_class_ops *rtc_ops;
+ struct rx8010_data *rx8010;
+ int err = 0;
+
+@@ -447,16 +457,16 @@ static int rx8010_probe(struct i2c_clien
+
+ if (err) {
+ dev_err(&client->dev, "unable to request IRQ\n");
+- client->irq = 0;
+- } else {
+- rx8010_rtc_ops.read_alarm = rx8010_read_alarm;
+- rx8010_rtc_ops.set_alarm = rx8010_set_alarm;
+- rx8010_rtc_ops.alarm_irq_enable = rx8010_alarm_irq_enable;
++ return err;
+ }
++
++ rtc_ops = &rx8010_rtc_ops_alarm;
++ } else {
++ rtc_ops = &rx8010_rtc_ops_default;
+ }
+
+ rx8010->rtc = devm_rtc_device_register(&client->dev, client->name,
+- &rx8010_rtc_ops, THIS_MODULE);
++ rtc_ops, THIS_MODULE);
+
+ if (IS_ERR(rx8010->rtc)) {
+ dev_err(&client->dev, "unable to register the class device\n");
ubifs-fix-a-memleak-after-dumping-authentication-mount-options.patch
ubifs-don-t-parse-authentication-mount-options-in-remount-process.patch
ubifs-mount_ubifs-release-authentication-resource-in-error-handling-path.patch
+perf-vendor-events-amd-add-l2-prefetch-events-for-zen1.patch
+perf-python-scripting-fix-printable-strings-in-python3-scripts.patch
+arc-perf-redo-the-pct-irq-missing-in-device-tree-handling.patch
+ubi-check-kthread_should_stop-after-the-setting-of-task-state.patch
+ia64-fix-build-error-with-coredump.patch
+rtc-rx8010-don-t-modify-the-global-rtc-ops.patch
+i2c-imx-fix-external-abort-on-interrupt-in-exit-paths.patch
+drm-amdgpu-don-t-map-bo-in-reserved-region.patch
+drm-amd-display-fix-incorrect-backlight-register-offset-for-dcn.patch
+drm-amd-display-increase-timeout-for-dp-disable.patch
+drm-amdgpu-vcn-and-jpeg-ring-synchronization.patch
+drm-amdgpu-update-golden-setting-for-sienna_cichlid.patch
+drm-amdgpu-correct-the-gpu-reset-handling-for-job-null-case.patch
+drm-amdkfd-use-same-sq-prefetch-setting-as-amdgpu.patch
+drm-amd-display-avoid-mst-manager-resource-leak.patch
--- /dev/null
+From d005f8c6588efcfbe88099b6edafc6f58c84a9c1 Mon Sep 17 00:00:00 2001
+From: Zhihao Cheng <chengzhihao1@huawei.com>
+Date: Mon, 1 Jun 2020 17:12:31 +0800
+Subject: ubi: check kthread_should_stop() after the setting of task state
+
+From: Zhihao Cheng <chengzhihao1@huawei.com>
+
+commit d005f8c6588efcfbe88099b6edafc6f58c84a9c1 upstream.
+
+A detach hung is possible when a race occurs between the detach process
+and the ubi background thread. The following sequences outline the race:
+
+ ubi thread: if (list_empty(&ubi->works)...
+
+ ubi detach: set_bit(KTHREAD_SHOULD_STOP, &kthread->flags)
+ => by kthread_stop()
+ wake_up_process()
+ => ubi thread is still running, so 0 is returned
+
+ ubi thread: set_current_state(TASK_INTERRUPTIBLE)
+ schedule()
+ => ubi thread will never be scheduled again
+
+ ubi detach: wait_for_completion()
+ => hung task!
+
+To fix that, we need to check kthread_should_stop() after we set the
+task state, so the ubi thread will either see the stop bit and exit or
+the task state is reset to runnable such that it isn't scheduled out
+indefinitely.
+
+Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com>
+Cc: <stable@vger.kernel.org>
+Fixes: 801c135ce73d5df1ca ("UBI: Unsorted Block Images")
+Reported-by: syzbot+853639d0cb16c31c7a14@syzkaller.appspotmail.com
+Signed-off-by: Richard Weinberger <richard@nod.at>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mtd/ubi/wl.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/mtd/ubi/wl.c
++++ b/drivers/mtd/ubi/wl.c
+@@ -1639,6 +1639,19 @@ int ubi_thread(void *u)
+ !ubi->thread_enabled || ubi_dbg_is_bgt_disabled(ubi)) {
+ set_current_state(TASK_INTERRUPTIBLE);
+ spin_unlock(&ubi->wl_lock);
++
++ /*
++ * Check kthread_should_stop() after we set the task
++ * state to guarantee that we either see the stop bit
++ * and exit or the task state is reset to runnable such
++ * that it's not scheduled out indefinitely and detects
++ * the stop bit at kthread_should_stop().
++ */
++ if (kthread_should_stop()) {
++ set_current_state(TASK_RUNNING);
++ break;
++ }
++
+ schedule();
+ continue;
+ }
projects / thirdparty / kernel / stable-queue.git / commitdiff
