drm/msm/a6xx: Use barriers while updating HFI Q headers

To avoid harmful compiler optimizations and IO reordering in the HW, use
barriers and READ/WRITE_ONCE helpers as necessary while accessing the HFI
queue index variables.

Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714653/
Message-ID: <20260327-a8xx-gpu-batch2-v2-1-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 53cfdf4e6c346857cff08ad644e868a1c6c13000..4f5dbf46132ba7d60a6277a38fce19fcd6cdda07 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -34,7 +34,7 @@ static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu,
        struct a6xx_hfi_queue_header *header = queue->header;
        u32 i, hdr, index = header->read_index;
 
-       if (header->read_index == header->write_index) {
+       if (header->read_index == READ_ONCE(header->write_index)) {
                header->rx_request = 1;
                return 0;
        }
@@ -62,7 +62,10 @@ static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu,
        if (!gmu->legacy)
                index = ALIGN(index, 4) % header->size;
 
-       header->read_index = index;
+       /* Ensure all memory operations are complete before updating the read index */
+       dma_mb();
+
+       WRITE_ONCE(header->read_index, index);
        return HFI_HEADER_SIZE(hdr);
 }
 
@@ -74,7 +77,7 @@ static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu,
 
        spin_lock(&queue->lock);
 
-       space = CIRC_SPACE(header->write_index, header->read_index,
+       space = CIRC_SPACE(header->write_index, READ_ONCE(header->read_index),
                header->size);
        if (space < dwords) {
                header->dropped++;
@@ -95,7 +98,10 @@ static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu,
                        queue->data[index] = 0xfafafafa;
        }
 
-       header->write_index = index;
+       /* Ensure all memory operations are complete before updating the write index */
+       dma_mb();
+
+       WRITE_ONCE(header->write_index, index);
        spin_unlock(&queue->lock);
 
        gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01);