phy: mscc: Fix parsing of unicast frames

[ Upstream commit 6fb5ff63b35b7e849cc8510957f25753f87f63d2 ]

According to the 1588 standard, it is possible to use both unicast and
multicast frames to send the PTP information. It was noticed that if the
frames were unicast they were not processed by the analyzer meaning that
they were not timestamped. Therefore fix this to match also these
unicast frames.

Fixes: ab2bf9339357 ("net: phy: mscc: 1588 block initialization")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250726140307.3039694-1-horatiu.vultur@microchip.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/phy/mscc/mscc_ptp.c b/drivers/net/phy/mscc/mscc_ptp.c
index 85102e895665e5298e617a38d7a0b3d317d45291..4a00b82d3ca5c21a7b22452131833d365d5598dc 100644 (file)
--- a/drivers/net/phy/mscc/mscc_ptp.c
+++ b/drivers/net/phy/mscc/mscc_ptp.c
@@ -897,6 +897,7 @@ static int vsc85xx_eth1_conf(struct phy_device *phydev, enum ts_blk blk,
                                     get_unaligned_be32(ptp_multicast));
        } else {
                val |= ANA_ETH1_FLOW_ADDR_MATCH2_ANY_MULTICAST;
+               val |= ANA_ETH1_FLOW_ADDR_MATCH2_ANY_UNICAST;
                vsc85xx_ts_write_csr(phydev, blk,
                                     MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), val);
                vsc85xx_ts_write_csr(phydev, blk,

diff --git a/drivers/net/phy/mscc/mscc_ptp.h b/drivers/net/phy/mscc/mscc_ptp.h
index 3ea163af0f4f4ba91a981a6da0951ff831e741e9..7e3809e4aa5f526ab4c5581d1682afe431a71677 100644 (file)
--- a/drivers/net/phy/mscc/mscc_ptp.h
+++ b/drivers/net/phy/mscc/mscc_ptp.h
@@ -98,6 +98,7 @@
 #define MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 3)
 #define ANA_ETH1_FLOW_ADDR_MATCH2_MASK_MASK    GENMASK(22, 20)
 #define ANA_ETH1_FLOW_ADDR_MATCH2_ANY_MULTICAST        0x400000
+#define ANA_ETH1_FLOW_ADDR_MATCH2_ANY_UNICAST  0x200000
 #define ANA_ETH1_FLOW_ADDR_MATCH2_FULL_ADDR    0x100000
 #define ANA_ETH1_FLOW_ADDR_MATCH2_SRC_DEST_MASK        GENMASK(17, 16)
 #define ANA_ETH1_FLOW_ADDR_MATCH2_SRC_DEST     0x020000