arm64: imx8ulp: Split SRAM0 mapping to isolate the SCMI shared memory as non-cacheable

This patch splits the 2MB SRAM0 mapping into three regions:
- 0x22000000~0x2201f000: cacheable normal memory
- 0x2201f000~0x22020000: non-cacheable device memory
- 0x22020000~0x22200000: cacheable normal memory

The change ensures the SCMI shared memory is non-cacheable, which
avoids cache-related issues after removing
mmu_set_region_dcache_behaviour() from scmi_dt_get_smt_buffer().

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 04c6f0641304d2794bc44beab4288b6964b0a4ef..1ee483065e85e223438f83e9625fd237f3c5ebdb 100644 (file)
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -384,7 +384,22 @@ static struct mm_region imx8ulp_arm64_mem_map[] = {
                /* SRAM0 (align with 2M) */
                .virt = 0x22000000UL,
                .phys = 0x22000000UL,
-               .size = 0x200000UL,
+               .size = 0x1f000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_OUTER_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* SCMI shared memory buffer must be mapped as non-cacheable. */
+               .virt = 0x2201f000UL,
+               .phys = 0x2201f000UL,
+               .size = 0x1000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               .virt = 0x22020000UL,
+               .phys = 0x22020000UL,
+               .size = 0x1e0000UL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
                         PTE_BLOCK_OUTER_SHARE |
                         PTE_BLOCK_PXN | PTE_BLOCK_UXN