drm/amd/display: use full update for clip size increase of large plane source

[ Upstream commit 05b78277ef0efc1deebc8a22384fffec29a3676e ]

[why]
Clip size increase will increase viewport, which could cause us to
switch  to MPC combine.
If we skip full update, we are not able to change to MPC combine in
fast update. This will cause corruption showing on the video plane.

[how]
treat clip size increase of a surface larger than 5k as a full update.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 14c3c1907b953e1ff082827dc1c24d07b19d41fe..38abbd0c9d99707b064b0c257f13322d999e3abc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -990,7 +990,8 @@ static bool dc_construct(struct dc *dc,
        /* set i2c speed if not done by the respective dcnxxx__resource.c */
        if (dc->caps.i2c_speed_in_khz_hdcp == 0)
                dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
-
+       if (dc->caps.max_optimizable_video_width == 0)
+               dc->caps.max_optimizable_video_width = 5120;
        dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
        if (!dc->clk_mgr)
                goto fail;
@@ -2442,6 +2443,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
 }
 
 static enum surface_update_type get_scaling_info_update_type(
+               const struct dc *dc,
                const struct dc_surface_update *u)
 {
        union surface_update_flags *update_flags = &u->surface->update_flags;
@@ -2474,6 +2476,12 @@ static enum surface_update_type get_scaling_info_update_type(
                        update_flags->bits.clock_change = 1;
        }
 
+       if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width &&
+               (u->scaling_info->clip_rect.width > u->surface->clip_rect.width ||
+                u->scaling_info->clip_rect.height > u->surface->clip_rect.height))
+                /* Changing clip size of a large surface may result in MPC slice count change */
+               update_flags->bits.bandwidth_change = 1;
+
        if (u->scaling_info->src_rect.x != u->surface->src_rect.x
                        || u->scaling_info->src_rect.y != u->surface->src_rect.y
                        || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
@@ -2511,7 +2519,7 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
        type = get_plane_info_update_type(u);
        elevate_update_type(&overall_type, type);
 
-       type = get_scaling_info_update_type(u);
+       type = get_scaling_info_update_type(dc, u);
        elevate_update_type(&overall_type, type);
 
        if (u->flip_addr) {

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 31e3183497a7f50a1e141286b1183f3ad76909a5..c05e91b257aceaeb63b1bd34c0303eb6e69964d1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -231,6 +231,11 @@ struct dc_caps {
        uint32_t dmdata_alloc_size;
        unsigned int max_cursor_size;
        unsigned int max_video_width;
+       /*
+        * max video plane width that can be safely assumed to be always
+        * supported by single DPP pipe.
+        */
+       unsigned int max_optimizable_video_width;
        unsigned int min_horizontal_blanking_period;
        int linear_pitch_alignment;
        bool dcc_const_color;