[AArch64][1/2] Remove UNSPEC_CLS and use clrsb RTL code in its' place.

	* config/aarch64/aarch64.md: Delete UNSPEC_CLS.
	(clrsb<mode>2): Use clrsb RTL code instead of UNSPEC_CLS.

From-SVN: r212912

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2d7f1e0168def9f2d55a6b0254324c38d8dc95c3..5c972bb462be2f31321f66bf9346ed61e03d0a10 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2014-07-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/aarch64.md: Delete UNSPEC_CLS.
+       (clrsb<mode>2): Use clrsb RTL code instead of UNSPEC_CLS.
+
 2014-07-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * config/aarch64/arm_neon.h (vbsl_f64): New intrinsic.

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 042a3b57756caafedf546ce182ced4e176f37148..0adec11dc7b212b94ce14481b7e59e69a2638dd5 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -67,7 +67,6 @@
 
 (define_c_enum "unspec" [
     UNSPEC_CASESI
-    UNSPEC_CLS
     UNSPEC_CRC32B
     UNSPEC_CRC32CB
     UNSPEC_CRC32CH
@@ -2863,7 +2862,7 @@
 
 (define_insn "clrsb<mode>2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
-       (unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_CLS))]
+        (clrsb:GPI (match_operand:GPI 1 "register_operand" "r")))]
   ""
   "cls\\t%<w>0, %<w>1"
   [(set_attr "type" "clz")]