arm64: dts: qcom: lemans: Add SDHC controller and SDC pin configuration

Introduce the SDHC v5 controller node for the Lemans platform.
This controller supports either eMMC or SD-card, but only one
can be active at a time. SD-card is the preferred configuration
on Lemans targets, so describe this controller.

Define the SDC interface pins including clk, cmd, and data lines
to enable proper communication with the SDHC controller.

Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Co-developed-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-1-53d7d206669d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index fd6eb6fbe29a177d5323a2f58ed85c35750c26aa..b7e727f01cec348305259dd2ddfb1520e028449c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -3835,6 +3835,58 @@
                        };
                };
 
+               sdhc: mmc@87c4000 {
+                       compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5";
+                       reg = <0x0 0x087c4000 0x0 0x1000>;
+
+                       interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hc_irq",
+                                         "pwr_irq";
+
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>;
+                       clock-names = "iface",
+                                     "core";
+
+                       interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "sdhc-ddr",
+                                            "cpu-sdhc";
+
+                       iommus = <&apps_smmu 0x0 0x0>;
+                       dma-coherent;
+
+                       operating-points-v2 = <&sdhc_opp_table>;
+                       power-domains = <&rpmhpd SA8775P_CX>;
+                       resets = <&gcc GCC_SDCC1_BCR>;
+
+                       qcom,dll-config = <0x0007642c>;
+                       qcom,ddr-config = <0x80040868>;
+
+                       status = "disabled";
+
+                       sdhc_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-100000000 {
+                                       opp-hz = /bits/ 64 <100000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <1800000 400000>;
+                                       opp-avg-kBps = <100000 0>;
+                               };
+
+                               opp-384000000 {
+                                       opp-hz = /bits/ 64 <384000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                                       opp-peak-kBps = <5400000 1600000>;
+                                       opp-avg-kBps = <390000 0>;
+                               };
+                       };
+               };
+
                usb_0_hsphy: phy@88e4000 {
                        compatible = "qcom,sa8775p-usb-hs-phy",
                                     "qcom,usb-snps-hs-5nm-phy";
@@ -5658,6 +5710,46 @@
                                        function = "qup3_se0";
                                };
                        };
+
+                       sdc_default: sdc-default-state {
+                               clk-pins {
+                                       pins = "sdc1_clk";
+                                       drive-strength = <16>;
+                                       bias-disable;
+                               };
+
+                               cmd-pins {
+                                       pins = "sdc1_cmd";
+                                       drive-strength = <10>;
+                                       bias-pull-up;
+                               };
+
+                               data-pins {
+                                       pins = "sdc1_data";
+                                       drive-strength = <10>;
+                                       bias-pull-up;
+                               };
+                       };
+
+                       sdc_sleep: sdc-sleep-state {
+                               clk-pins {
+                                       pins = "sdc1_clk";
+                                       drive-strength = <2>;
+                                       bias-bus-hold;
+                               };
+
+                               cmd-pins {
+                                       pins = "sdc1_cmd";
+                                       drive-strength = <2>;
+                                       bias-bus-hold;
+                               };
+
+                               data-pins {
+                                       pins = "sdc1_data";
+                                       drive-strength = <2>;
+                                       bias-bus-hold;
+                               };
+                       };
                };
 
                sram: sram@146d8000 {