KVM: x86/speculation: Disable Fill buffer clear within guests

commit 027bbb884be006b05d9c577d6401686053aa789e upstream

The enumeration of MD_CLEAR in CPUID(EAX=7,ECX=0).EDX{bit 10} is not an
accurate indicator on all CPUs of whether the VERW instruction will
overwrite fill buffers. FB_CLEAR enumeration in
IA32_ARCH_CAPABILITIES{bit 17} covers the case of CPUs that are not
vulnerable to MDS/TAA, indicating that microcode does overwrite fill
buffers.

Guests running in VMM environments may not be aware of all the
capabilities/vulnerabilities of the host CPU. Specifically, a guest may
apply MDS/TAA mitigations when a virtual CPU is enumerated as vulnerable
to MDS/TAA even when the physical CPU is not. On CPUs that enumerate
FB_CLEAR_CTRL the VMM may set FB_CLEAR_DIS to skip overwriting of fill
buffers by the VERW instruction. This is done by setting FB_CLEAR_DIS
during VMENTER and resetting on VMEXIT. For guests that enumerate
FB_CLEAR (explicitly asking for fill buffer clear capability) the VMM
will not use FB_CLEAR_DIS.

Irrespective of guest state, host overwrites CPU buffers before VMENTER
to protect itself from an MMIO capable guest, as part of mitigation for
MMIO Stale Data vulnerabilities.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
[cascardo: arch/x86/kvm/vmx.c has been split and context adjustment at
 vmx_vcpu_run]
[cascardo: moved functions so they are after struct vcpu_vmx definition]
[cascardo: fb_clear is disabled/enabled around __vmx_vcpu_run]
Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index d30f2a7d00bc7ea0d458c4484cada9fd1add5751..586be095ed08135d07c5d8d519e7452e05a8e906 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -115,6 +115,11 @@
                                                 * VERW clears CPU fill buffer
                                                 * even on MDS_NO CPUs.
                                                 */
+#define ARCH_CAP_FB_CLEAR_CTRL         BIT(18) /*
+                                                * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
+                                                * bit available to control VERW
+                                                * behavior.
+                                                */
 
 #define MSR_IA32_FLUSH_CMD             0x0000010b
 #define L1D_FLUSH                      BIT(0)  /*
@@ -132,6 +137,7 @@
 /* SRBDS support */
 #define MSR_IA32_MCU_OPT_CTRL          0x00000123
 #define RNGDS_MITG_DIS                 BIT(0)
+#define FB_CLEAR_DIS                   BIT(3)  /* CPU Fill buffer clear disable */
 
 #define MSR_IA32_SYSENTER_CS           0x00000174
 #define MSR_IA32_SYSENTER_ESP          0x00000175

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index bf6934352e3a41c36e1b20206c21e1e7daefd171..44cce3e8eb18bfc38646e3f8e854e544a3a6d382 100644 (file)
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -212,6 +212,9 @@ static const struct {
 #define L1D_CACHE_ORDER 4
 static void *vmx_l1d_flush_pages;
 
+/* Control for disabling CPU Fill buffer clear */
+static bool __read_mostly vmx_fb_clear_ctrl_available;
+
 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 {
        struct page *page;
@@ -1045,6 +1048,8 @@ struct vcpu_vmx {
        u64 msr_ia32_feature_control;
        u64 msr_ia32_feature_control_valid_bits;
        u64 ept_pointer;
+       u64 msr_ia32_mcu_opt_ctrl;
+       bool disable_fb_clear;
 };
 
 enum segment_cache_field {
@@ -2107,6 +2112,60 @@ static inline void __invept(unsigned long ext, u64 eptp, gpa_t gpa)
        BUG_ON(error);
 }
 
+static void vmx_setup_fb_clear_ctrl(void)
+{
+       u64 msr;
+
+       if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES) &&
+           !boot_cpu_has_bug(X86_BUG_MDS) &&
+           !boot_cpu_has_bug(X86_BUG_TAA)) {
+               rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
+               if (msr & ARCH_CAP_FB_CLEAR_CTRL)
+                       vmx_fb_clear_ctrl_available = true;
+       }
+}
+
+static __always_inline void vmx_disable_fb_clear(struct vcpu_vmx *vmx)
+{
+       u64 msr;
+
+       if (!vmx->disable_fb_clear)
+               return;
+
+       rdmsrl(MSR_IA32_MCU_OPT_CTRL, msr);
+       msr |= FB_CLEAR_DIS;
+       wrmsrl(MSR_IA32_MCU_OPT_CTRL, msr);
+       /* Cache the MSR value to avoid reading it later */
+       vmx->msr_ia32_mcu_opt_ctrl = msr;
+}
+
+static __always_inline void vmx_enable_fb_clear(struct vcpu_vmx *vmx)
+{
+       if (!vmx->disable_fb_clear)
+               return;
+
+       vmx->msr_ia32_mcu_opt_ctrl &= ~FB_CLEAR_DIS;
+       wrmsrl(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl);
+}
+
+static void vmx_update_fb_clear_dis(struct kvm_vcpu *vcpu, struct vcpu_vmx *vmx)
+{
+       vmx->disable_fb_clear = vmx_fb_clear_ctrl_available;
+
+       /*
+        * If guest will not execute VERW, there is no need to set FB_CLEAR_DIS
+        * at VMEntry. Skip the MSR read/write when a guest has no use case to
+        * execute VERW.
+        */
+       if ((vcpu->arch.arch_capabilities & ARCH_CAP_FB_CLEAR) ||
+          ((vcpu->arch.arch_capabilities & ARCH_CAP_MDS_NO) &&
+           (vcpu->arch.arch_capabilities & ARCH_CAP_TAA_NO) &&
+           (vcpu->arch.arch_capabilities & ARCH_CAP_PSDP_NO) &&
+           (vcpu->arch.arch_capabilities & ARCH_CAP_FBSDP_NO) &&
+           (vcpu->arch.arch_capabilities & ARCH_CAP_SBDR_SSDP_NO)))
+               vmx->disable_fb_clear = false;
+}
+
 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 {
        int i;
@@ -4314,9 +4373,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                        }
                        break;
                }
-               ret = kvm_set_msr_common(vcpu, msr_info);
+                       ret = kvm_set_msr_common(vcpu, msr_info);
        }
 
+       /* FB_CLEAR may have changed, also update the FB_CLEAR_DIS behavior */
+       if (msr_index == MSR_IA32_ARCH_CAPABILITIES)
+               vmx_update_fb_clear_dis(vcpu, vmx);
+
        return ret;
 }
 
@@ -6761,6 +6824,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
        vpid_sync_context(vmx->vpid);
        if (init_event)
                vmx_clear_hlt(vcpu);
+
+       vmx_update_fb_clear_dis(vcpu, vmx);
 }
 
 /*
@@ -10777,6 +10842,8 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
                 kvm_arch_has_assigned_device(vcpu->kvm))
                mds_clear_cpu_buffers();
 
+       vmx_disable_fb_clear(vmx);
+
        asm volatile (
                /* Store host registers */
                "push %%" _ASM_DX "; push %%" _ASM_BP ";"
@@ -10921,6 +10988,8 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
 #endif
              );
 
+       vmx_enable_fb_clear(vmx);
+
        /*
         * We do not use IBRS in the kernel. If this vCPU has used the
         * SPEC_CTRL MSR it may have left it on; save the value and
@@ -14626,8 +14695,11 @@ static int __init vmx_init(void)
                }
        }
 
+       vmx_setup_fb_clear_ctrl();
+
        for_each_possible_cpu(cpu) {
                INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
+
                INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
                spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
        }

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 417abc9ba1ad4008e14c07fb3d5cfc64094d0503..be4697d91bb24093a63d04367f5a039d61232fd6 100644 (file)
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1220,6 +1220,10 @@ u64 kvm_get_arch_capabilities(void)
 
        /* KVM does not emulate MSR_IA32_TSX_CTRL.  */
        data &= ~ARCH_CAP_TSX_CTRL_MSR;
+
+       /* Guests don't need to know "Fill buffer clear control" exists */
+       data &= ~ARCH_CAP_FB_CLEAR_CTRL;
+
        return data;
 }