ARM64: zynqmp: Updated dts for pin control

Added pin control support in dts for
zynqmp-zc1751-xm015-dc1
zynqmp-zc1751-xm016-dc2
zynqmp-zc1751-xm019-dc5
zynqmp-zcu106

Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 5fa9c6c071fc6caa372f0644d8a5d50dd2eebe87..3eca6790f16fd3bf16e2e294b86ff23962c280b9 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -13,6 +13,8 @@
 #include "zynqmp.dtsi"
 #include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/phy/phy.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 
 / {
        model = "ZynqMP zc1751-xm015-dc1 RevA";
@@ -87,6 +89,8 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gem3_default>;
        phy0: phy@0 {
                reg = <0>;
        };
@@ -94,6 +98,8 @@
 
 &gpio {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpio_default>;
 };
 
 &gpu {
@@ -103,6 +109,12 @@
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c1_default>;
+       pinctrl-1 = <&pinctrl_i2c1_gpio>;
+       scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
+       sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+
        eeprom@55 {
                compatible = "at,24c64"; /* 24AA64 */
                reg = <0x55>;
@@ -160,6 +172,8 @@
 /* eMMC */
 &sdhci0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sdhci0_default>;
        bus-width = <8>;
        xlnx,mio_bank = <0>;
 };
@@ -167,6 +181,8 @@
 /* SD1 with level shifter */
 &sdhci1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sdhci1_default>;
        no-1-8-v;       /* for 1.0 silicon */
        xlnx,mio_bank = <1>;
 };
@@ -177,11 +193,15 @@
 
 &uart0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0_default>;
 };
 
 /* ULPI SMSC USB3320 */
 &usb0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usb0_default>;
 };
 
 &dwc3_0 {
@@ -227,3 +247,212 @@
 &xlnx_dpdma {
        status = "okay";
 };
+
+&pinctrl0 {
+       pinctrl_i2c1_default: i2c1-default {
+               mux {
+                       groups = "i2c1_9_grp";
+                       function = "i2c1";
+               };
+
+               conf {
+                       groups = "i2c1_9_grp";
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c1_gpio: i2c1-gpio {
+               mux {
+                       groups = "gpio0_36_grp", "gpio0_37_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_36_grp", "gpio0_37_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_uart0_default: uart0-default {
+               mux {
+                       groups = "uart0_8_grp";
+                       function = "uart0";
+               };
+
+               conf {
+                       groups = "uart0_8_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO34";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO35";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_usb0_default: usb0-default {
+               mux {
+                       groups = "usb0_0_grp";
+                       function = "usb0";
+               };
+
+               conf {
+                       groups = "usb0_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO52", "MIO53", "MIO55";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+                              "MIO60", "MIO61", "MIO62", "MIO63";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_gem3_default: gem3-default {
+               mux {
+                       function = "ethernet3";
+                       groups = "ethernet3_0_grp";
+               };
+
+               conf {
+                       groups = "ethernet3_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+                                                                       "MIO75";
+                       bias-high-impedance;
+                       low-power-disable;
+               };
+
+               conf-tx {
+                       pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+                                                                       "MIO69";
+                       bias-disable;
+                       low-power-enable;
+               };
+
+               mux-mdio {
+                       function = "mdio3";
+                       groups = "mdio3_0_grp";
+               };
+
+               conf-mdio {
+                       groups = "mdio3_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+       };
+
+       pinctrl_sdhci0_default: sdhci0-default {
+               mux {
+                       groups = "sdio0_0_grp";
+                       function = "sdio0";
+               };
+
+               conf {
+                       groups = "sdio0_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+
+               mux-cd {
+                       groups = "sdio0_0_cd_grp";
+                       function = "sdio0_cd";
+               };
+
+               conf-cd {
+                       groups = "sdio0_0_cd_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux-wp {
+                       groups = "sdio0_0_wp_grp";
+                       function = "sdio0_wp";
+               };
+
+               conf-wp {
+                       groups = "sdio0_0_wp_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_sdhci1_default: sdhci1-default {
+               mux {
+                       groups = "sdio1_0_grp";
+                       function = "sdio1";
+               };
+
+               conf {
+                       groups = "sdio1_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+
+               mux-cd {
+                       groups = "sdio1_0_cd_grp";
+                       function = "sdio1_cd";
+               };
+
+               conf-cd {
+                       groups = "sdio1_0_cd_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux-wp {
+                       groups = "sdio1_0_wp_grp";
+                       function = "sdio1_wp";
+               };
+
+               conf-wp {
+                       groups = "sdio1_0_wp_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_gpio_default: gpio-default {
+               mux {
+                       function = "gpio0";
+                       groups = "gpio0_38_grp";
+               };
+
+               conf {
+                       groups = "gpio0_38_grp";
+                       bias-disable;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+};

diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 48cb1e7bb60a3d57c285594270905820448337c9..ce6057399cf5ecb7cc246e5544d0a295d18afd2e 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -12,6 +12,8 @@
 
 #include "zynqmp.dtsi"
 #include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 
 / {
        model = "ZynqMP zc1751-xm016-dc2 RevA";
@@ -44,10 +46,14 @@
 
 &can0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can0_default>;
 };
 
 &can1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can1_default>;
 };
 
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
@@ -96,6 +102,8 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gem2_default>;
        phy0: phy@5 {
                reg = <5>;
                ti,rx-internal-delay = <0x8>;
@@ -111,6 +119,11 @@
 &i2c0 {
        status = "okay";
        clock-frequency = <400000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c0_default>;
+       pinctrl-1 = <&pinctrl_i2c0_gpio>;
+       scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
+       sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 
        tca6416_u26: gpio@20 {
                compatible = "ti,tca6416";
@@ -128,6 +141,8 @@
 
 &nand0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_nand0_default>;
        arasan,has-mdma;
 
        nand@0 {
@@ -199,6 +214,9 @@
 &spi0 {
        status = "okay";
        num-cs = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_spi0_default>;
+
        spi0_flash0: spi0_flash0@0 {
                compatible = "m25p80";
                #address-cells = <1>;
@@ -216,6 +234,9 @@
 &spi1 {
        status = "okay";
        num-cs = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_spi1_default>;
+
        spi1_flash0: spi1_flash0@0 {
                compatible = "mtd_dataflash";
                #address-cells = <1>;
@@ -233,6 +254,8 @@
 /* ULPI SMSC USB3320 */
 &usb1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usb1_default>;
 };
 
 &dwc3_1 {
@@ -242,8 +265,290 @@
 
 &uart0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0_default>;
 };
 
 &uart1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1_default>;
+};
+
+&pinctrl0 {
+       pinctrl_can0_default: can0-default {
+               mux {
+                       function = "can0";
+                       groups = "can0_9_grp";
+               };
+
+               conf {
+                       groups = "can0_9_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO38";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO39";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_can1_default: can1-default {
+               mux {
+                       function = "can1";
+                       groups = "can1_8_grp";
+               };
+
+               conf {
+                       groups = "can1_8_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO33";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO32";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_i2c0_default: i2c0-default {
+               mux {
+                       groups = "i2c0_1_grp";
+                       function = "i2c0";
+               };
+
+               conf {
+                       groups = "i2c0_1_grp";
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c0_gpio: i2c0-gpio {
+               mux {
+                       groups = "gpio0_6_grp", "gpio0_7_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_6_grp", "gpio0_7_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_uart0_default: uart0-default {
+               mux {
+                       groups = "uart0_10_grp";
+                       function = "uart0";
+               };
+
+               conf {
+                       groups = "uart0_10_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO42";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO43";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_uart1_default: uart1-default {
+               mux {
+                       groups = "uart1_10_grp";
+                       function = "uart1";
+               };
+
+               conf {
+                       groups = "uart1_10_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO41";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO40";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_usb1_default: usb1-default {
+               mux {
+                       groups = "usb1_0_grp";
+                       function = "usb1";
+               };
+
+               conf {
+                       groups = "usb1_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO64", "MIO65", "MIO67";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+                              "MIO72", "MIO73", "MIO74", "MIO75";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_gem2_default: gem2-default {
+               mux {
+                       function = "ethernet2";
+                       groups = "ethernet2_0_grp";
+               };
+
+               conf {
+                       groups = "ethernet2_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
+                                                                       "MIO63";
+                       bias-high-impedance;
+                       low-power-disable;
+               };
+
+               conf-tx {
+                       pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
+                                                                       "MIO57";
+                       bias-disable;
+                       low-power-enable;
+               };
+
+               mux-mdio {
+                       function = "mdio2";
+                       groups = "mdio2_0_grp";
+               };
+
+               conf-mdio {
+                       groups = "mdio2_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+       };
+
+       pinctrl_nand0_default: nand0-default {
+               mux {
+                       groups = "nand0_0_grp";
+                       function = "nand0";
+               };
+
+               conf {
+                       groups = "nand0_0_grp";
+                       bias-pull-up;
+               };
+
+               mux-ce {
+                       groups = "nand0_0_ce_grp";
+                       function = "nand0_ce";
+               };
+
+               conf-ce {
+                       groups = "nand0_0_ce_grp";
+                       bias-pull-up;
+               };
+
+               mux-rb {
+                       groups = "nand0_0_rb_grp";
+                       function = "nand0_rb";
+               };
+
+               conf-rb {
+                       groups = "nand0_0_rb_grp";
+                       bias-pull-up;
+               };
+
+               mux-dqs {
+                       groups = "nand0_0_dqs_grp";
+                       function = "nand0_dqs";
+               };
+
+               conf-dqs {
+                       groups = "nand0_0_dqs_grp";
+                       bias-pull-up;
+               };
+       };
+
+       pinctrl_spi0_default: spi0-default {
+               mux {
+                       groups = "spi0_0_grp";
+                       function = "spi0";
+               };
+
+               conf {
+                       groups = "spi0_0_grp";
+                       bias-disable;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux-cs {
+                       groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp",
+                                                       "spi0_0_ss2_grp";
+                       function = "spi0_ss";
+               };
+
+               conf-cs {
+                       groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp",
+                                                       "spi0_0_ss2_grp";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_spi1_default: spi1-default {
+               mux {
+                       groups = "spi1_3_grp";
+                       function = "spi1";
+               };
+
+               conf {
+                       groups = "spi1_3_grp";
+                       bias-disable;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux-cs {
+                       groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp",
+                                                       "spi1_3_ss2_grp";
+                       function = "spi1_ss";
+               };
+
+               conf-cs {
+                       groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp",
+                                                       "spi1_3_ss2_grp";
+                       bias-disable;
+               };
+       };
 };

diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 465e64e9bd40ff8552b230bee4ea6acd0b07c8a0..469375e507545ea4a6f0ed712a776444939e32e4 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -13,6 +13,9 @@
 
 #include "zynqmp.dtsi"
 #include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
 / {
        model = "ZynqMP zc1751-xm019-dc5 RevA";
        compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
@@ -84,6 +87,8 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gem1_default>;
        phy0: phy@0 {
                reg = <0>;
        };
@@ -96,25 +101,364 @@
 /* FIXME: Add device */
 &i2c0 {
        status = "okay";
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c0_default>;
+       pinctrl-1 = <&pinctrl_i2c0_gpio>;
+       scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
+       sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
 };
 
 /* FIXME: Add device */
 &i2c1 {
        status = "okay";
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c1_default>;
+       pinctrl-1 = <&pinctrl_i2c1_gpio>;
+       scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
+       sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
+
 };
 
 &sdhci0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sdhci0_default>;
 };
 
 &uart0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0_default>;
 };
 
 &uart1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
 &watchdog0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_watchdog0_default>;
+};
+
+&ttc0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ttc0_default>;
+};
+
+&ttc1 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ttc1_default>;
+};
+
+&ttc2 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ttc2_default>;
+};
+
+&ttc3 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ttc3_default>;
+};
+
+&pinctrl0 {
+       pinctrl_i2c0_default: i2c0-default {
+               mux {
+                       groups = "i2c0_18_grp";
+                       function = "i2c0";
+               };
+
+               conf {
+                       groups = "i2c0_18_grp";
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c0_gpio: i2c0-gpio {
+               mux {
+                       groups = "gpio0_74_grp", "gpio0_75_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_74_grp", "gpio0_75_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c1_default: i2c1-default {
+               mux {
+                       groups = "i2c1_19_grp";
+                       function = "i2c1";
+               };
+
+               conf {
+                       groups = "i2c1_19_grp";
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c1_gpio: i2c1-gpio {
+               mux {
+                       groups = "gpio0_76_grp", "gpio0_77_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_76_grp", "gpio0_77_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_uart0_default: uart0-default {
+               mux {
+                       groups = "uart0_17_grp";
+                       function = "uart0";
+               };
+
+               conf {
+                       groups = "uart0_17_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO70";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO71";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_uart1_default: uart1-default {
+               mux {
+                       groups = "uart1_18_grp";
+                       function = "uart1";
+               };
+
+               conf {
+                       groups = "uart1_18_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO73";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO72";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_gem1_default: gem1-default {
+               mux {
+                       function = "ethernet1";
+                       groups = "ethernet1_0_grp";
+               };
+
+               conf {
+                       groups = "ethernet1_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
+                                                                       "MIO49";
+                       bias-high-impedance;
+                       low-power-disable;
+               };
+
+               conf-tx {
+                       pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
+                                                                       "MIO43";
+                       bias-disable;
+                       low-power-enable;
+               };
+
+               mux-mdio {
+                       function = "mdio1";
+                       groups = "mdio1_0_grp";
+               };
+
+               conf-mdio {
+                       groups = "mdio1_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+       };
+
+       pinctrl_sdhci0_default: sdhci0-default {
+               mux {
+                       groups = "sdio0_0_grp";
+                       function = "sdio0";
+               };
+
+               conf {
+                       groups = "sdio0_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+
+               mux-cd {
+                       groups = "sdio0_0_cd_grp";
+                       function = "sdio0_cd";
+               };
+
+               conf-cd {
+                       groups = "sdio0_0_cd_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux-wp {
+                       groups = "sdio0_0_wp_grp";
+                       function = "sdio0_wp";
+               };
+
+               conf-wp {
+                       groups = "sdio0_0_wp_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_watchdog0_default: watchdog0-default {
+               mux-clk {
+                       groups = "swdt0_1_clk_grp";
+                       function = "swdt0_clk";
+               };
+
+               conf-clk {
+                       groups = "swdt0_1_clk_grp";
+                       bias-pull-up;
+               };
+
+               mux-rst {
+                       groups = "swdt0_1_rst_grp";
+                       function = "swdt0_rst";
+               };
+
+               conf-rst {
+                       groups = "swdt0_1_rst_grp";
+                       bias-disable;
+                       slew-rate = <SLEW_RATE_SLOW>;
+               };
+       };
+
+       pinctrl_ttc0_default: ttc0-default {
+               mux-clk {
+                       groups = "ttc0_0_clk_grp";
+                       function = "ttc0_clk";
+               };
+
+               conf-clk {
+                       groups = "ttc0_0_clk_grp";
+                       bias-pull-up;
+               };
+
+               mux-wav {
+                       groups = "ttc0_0_wav_grp";
+                       function = "ttc0_wav";
+               };
+
+               conf-wav {
+                       groups = "ttc0_0_wav_grp";
+                       bias-disable;
+                       slew-rate = <SLEW_RATE_SLOW>;
+               };
+       };
+
+       pinctrl_ttc1_default: ttc1-default {
+               mux-clk {
+                       groups = "ttc1_0_clk_grp";
+                       function = "ttc1_clk";
+               };
+
+               conf-clk {
+                       groups = "ttc1_0_clk_grp";
+                       bias-pull-up;
+               };
+
+               mux-wav {
+                       groups = "ttc1_0_wav_grp";
+                       function = "ttc1_wav";
+               };
+
+               conf-wav {
+                       groups = "ttc1_0_wav_grp";
+                       bias-disable;
+                       slew-rate = <SLEW_RATE_SLOW>;
+               };
+       };
+
+       pinctrl_ttc2_default: ttc2-default {
+               mux-clk {
+                       groups = "ttc2_0_clk_grp";
+                       function = "ttc2_clk";
+               };
+
+               conf-clk {
+                       groups = "ttc2_0_clk_grp";
+                       bias-pull-up;
+               };
+
+               mux-wav {
+                       groups = "ttc2_0_wav_grp";
+                       function = "ttc2_wav";
+               };
+
+               conf-wav {
+                       groups = "ttc2_0_wav_grp";
+                       bias-disable;
+                       slew-rate = <SLEW_RATE_SLOW>;
+               };
+       };
+
+       pinctrl_ttc3_default: ttc3-default {
+               mux-clk {
+                       groups = "ttc3_0_clk_grp";
+                       function = "ttc3_clk";
+               };
+
+               conf-clk {
+                       groups = "ttc3_0_clk_grp";
+                       bias-pull-up;
+               };
+
+               mux-wav {
+                       groups = "ttc3_0_wav_grp";
+                       function = "ttc3_wav";
+               };
+
+               conf-wav {
+                       groups = "ttc3_0_wav_grp";
+                       bias-disable;
+                       slew-rate = <SLEW_RATE_SLOW>;
+               };
+       };
 };

diff --git a/arch/arm/dts/zynqmp-zcu106.dts b/arch/arm/dts/zynqmp-zcu106.dts
index a7d5f5b262e84d00e1ecfe8a9973bf0aee1574ab..f3552ab68913a14b7bdf2f5282431ba7d0ed6eda 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu106.dts
+++ b/arch/arm/dts/zynqmp-zcu106.dts
@@ -13,6 +13,7 @@
 #include "zynqmp.dtsi"
 #include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 #include <dt-bindings/phy/phy.h>
 
 / {
@@ -69,6 +70,8 @@
 
 &can1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can1_default>;
 };
 
 &dcc {
@@ -121,6 +124,8 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gem3_default>;
        phy0: phy@21 {
                reg = <21>;
                ti,rx-internal-delay = <0x8>;
@@ -131,6 +136,8 @@
 
 &gpio {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpio_default>;
 };
 
 &gpu {
@@ -140,6 +147,11 @@
 &i2c0 {
        status = "okay";
        clock-frequency = <400000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c0_default>;
+       pinctrl-1 = <&pinctrl_i2c0_gpio>;
+       scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+       sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 
        tca6416_u97: gpio@20 {
                /*
@@ -371,6 +383,12 @@
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c1_default>;
+       pinctrl-1 = <&pinctrl_i2c1_gpio>;
+       scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+       sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+
        /* FIXME PL i2c via PCA9306 - u45 */
        /* FIXME MSP430 - u41 - not detected */
        i2cswitch@74 { /* u34 */
@@ -581,6 +599,8 @@
 /* SD1 with level shifter */
 &sdhci1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sdhci1_default>;
        xlnx,mio_bank = <1>;
 };
 
@@ -590,15 +610,21 @@
 
 &uart0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0_default>;
 };
 
 &uart1 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
 /* ULPI SMSC USB3320 */
 &usb0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usb0_default>;
 };
 
 &dwc3_0 {
@@ -644,3 +670,265 @@
 &xlnx_dpdma {
        status = "okay";
 };
+
+&pinctrl0 {
+       pinctrl_i2c0_default: i2c0-default {
+               mux {
+                       groups = "i2c0_3_grp";
+                       function = "i2c0";
+               };
+
+               conf {
+                       groups = "i2c0_3_grp";
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c0_gpio: i2c0-gpio {
+               mux {
+                       groups = "gpio0_14_grp", "gpio0_15_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_14_grp", "gpio0_15_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c1_default: i2c1-default {
+               mux {
+                       groups = "i2c1_4_grp";
+                       function = "i2c1";
+               };
+
+               conf {
+                       groups = "i2c1_4_grp";
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_i2c1_gpio: i2c1-gpio {
+               mux {
+                       groups = "gpio0_16_grp", "gpio0_17_grp";
+                       function = "gpio0";
+               };
+
+               conf {
+                       groups = "gpio0_16_grp", "gpio0_17_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_uart0_default: uart0-default {
+               mux {
+                       groups = "uart0_4_grp";
+                       function = "uart0";
+               };
+
+               conf {
+                       groups = "uart0_4_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO18";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO19";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_uart1_default: uart1-default {
+               mux {
+                       groups = "uart1_5_grp";
+                       function = "uart1";
+               };
+
+               conf {
+                       groups = "uart1_5_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO21";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO20";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_usb0_default: usb0-default {
+               mux {
+                       groups = "usb0_0_grp";
+                       function = "usb0";
+               };
+
+               conf {
+                       groups = "usb0_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO52", "MIO53", "MIO55";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+                              "MIO60", "MIO61", "MIO62", "MIO63";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_gem3_default: gem3-default {
+               mux {
+                       function = "ethernet3";
+                       groups = "ethernet3_0_grp";
+               };
+
+               conf {
+                       groups = "ethernet3_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+                                                                       "MIO75";
+                       bias-high-impedance;
+                       low-power-disable;
+               };
+
+               conf-tx {
+                       pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+                                                                       "MIO69";
+                       bias-disable;
+                       low-power-enable;
+               };
+
+               mux-mdio {
+                       function = "mdio3";
+                       groups = "mdio3_0_grp";
+               };
+
+               conf-mdio {
+                       groups = "mdio3_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+       };
+
+       pinctrl_can1_default: can1-default {
+               mux {
+                       function = "can1";
+                       groups = "can1_6_grp";
+               };
+
+               conf {
+                       groups = "can1_6_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO25";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO24";
+                       bias-disable;
+               };
+       };
+
+       pinctrl_sdhci1_default: sdhci1-default {
+               mux {
+                       groups = "sdio1_0_grp";
+                       function = "sdio1";
+               };
+
+               conf {
+                       groups = "sdio1_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+               };
+
+               mux-cd {
+                       groups = "sdio1_0_cd_grp";
+                       function = "sdio1_cd";
+               };
+
+               conf-cd {
+                       groups = "sdio1_0_cd_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux-wp {
+                       groups = "sdio1_0_wp_grp";
+                       function = "sdio1_wp";
+               };
+
+               conf-wp {
+                       groups = "sdio1_0_wp_grp";
+                       bias-high-impedance;
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+       };
+
+       pinctrl_gpio_default: gpio-default {
+               mux {
+                       function = "gpio0";
+                       groups = "gpio0_22_grp", "gpio0_23_grp";
+               };
+
+               conf {
+                       groups = "gpio0_22_grp", "gpio0_23_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux-msp {
+                       function = "gpio0";
+                       groups = "gpio0_13_grp", "gpio0_38_grp";
+               };
+
+               conf-msp {
+                       groups = "gpio0_13_grp", "gpio0_38_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       io-standard = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-pull-up {
+                       pins = "MIO22";
+                       bias-pull-up;
+               };
+
+               conf-pull-none {
+                       pins = "MIO13", "MIO23", "MIO38";
+                       bias-disable;
+               };
+       };
+};