return 0;
}
+int spi_flash_set_qeb(struct spi_flash *flash)
+{
+ u8 qeb_status, cmd;
+ int ret;
+
+ cmd = CMD_READ_CONFIG;
+ ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
+ if (ret < 0) {
+ debug("SF: fail to read config register\n");
+ return ret;
+ }
+
+ if (qeb_status & STATUS_QEB) {
+ debug("SF: qeb is already set\n");
+ } else {
+ ret = spi_flash_cmd_write_config(flash, STATUS_QEB);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_SPI_FLASH_BAR
int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
goto err_manufacturer_probe;
#endif
+ /* set the quad enable bit - only for quad commands */
+ if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+ (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
+ if (spi_flash_set_qeb(flash)) {
+ debug("SF: Fail to set qeb\n");
+ goto err_manufacturer_probe;
+ }
+ }
+
#ifdef CONFIG_OF_CONTROL
if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
debug("SF: FDT decode error\n");
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS 0x05
+#define CMD_READ_CONFIG 0x35
#define CMD_FLAG_STATUS 0x70
#define CMD_WRITE_ENABLE 0x06
#define CMD_ERASE_4K 0x20
/* Common status */
#define STATUS_WIP 0x01
+#define STATUS_QEB 0x02
#define STATUS_PEC 0x80
/* Send a single-byte command to the device and read the response */