addInstr(env, X86Instr_Set32(cond,dst));
return dst;
}
+ case Iop_1Sto32: {
+ /* could do better than this, but for now ... */
+ HReg dst = newVRegI(env);
+ X86CondCode cond = iselCondCode(env, e->Iex.Unop.arg);
+ addInstr(env, X86Instr_Set32(cond,dst));
+ addInstr(env, X86Instr_Sh32(Xsh_SHL, 31, X86RM_Reg(dst)));
+ addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, X86RM_Reg(dst)));
+ return dst;
+ }
case Iop_Ctz32: {
/* Count trailing zeroes, implemented by x86 'bsfl' */
HReg dst = newVRegI(env);
addInstr(env, mk_MOVsd_RR(hregX86_EAX(),dstLo) );
return;
}
- if (retty == Ity_I32 || retty == Ity_I16) {
+ if (retty == Ity_I32 || retty == Ity_I16 || retty == Ity_I8) {
/* The returned value is in %eax. Park it in the register
associated with tmp. */
HReg dst = lookupIRTemp(env, d->tmp);
case Iop_32Uto64: vex_printf("32Uto64"); return;
case Iop_32to8: vex_printf("32to8"); return;
+ case Iop_And1: vex_printf("And1"); return;
+ case Iop_Or1: vex_printf("Or1"); return;
case Iop_Not1: vex_printf("Not1"); return;
case Iop_32to1: vex_printf("32to1"); return;
case Iop_1Uto8: vex_printf("1Uto8"); return;
case Iop_1Uto32: vex_printf("1Uto32"); return;
+ case Iop_1Sto32: vex_printf("1Sto32"); return;
case Iop_MullS8: vex_printf("MullS8"); return;
case Iop_MullS16: vex_printf("MullS16"); return;
case Iop_32HLto64:
BINARY(Ity_I64,Ity_I32,Ity_I32);
+ case Iop_And1:
+ case Iop_Or1: BINARY(Ity_Bit,Ity_Bit,Ity_Bit);
case Iop_Not1: UNARY(Ity_Bit,Ity_Bit);
case Iop_1Uto8: UNARY(Ity_I8,Ity_Bit);
- case Iop_1Uto32: UNARY(Ity_I32,Ity_Bit);
+ case Iop_1Uto32: case Iop_1Sto32: UNARY(Ity_I32,Ity_Bit);
case Iop_32to1: UNARY(Ity_Bit,Ity_I32);
case Iop_8Uto32: case Iop_8Sto32:
Iop_32HLto64, // :: (I32,I32) -> I64
/* 1-bit stuff */
Iop_Not1, /* :: Ity_Bit -> Ity_Bit */
+ Iop_Or1, /* :: Ity_Bit, Ity_Bit -> Ity_Bit */
+ Iop_And1, /* :: Ity_Bit, Ity_Bit -> Ity_Bit */
Iop_32to1, /* :: Ity_I32 -> Ity_Bit, just select bit[0] */
Iop_1Uto8, /* :: Ity_Bit -> Ity_I8, unsigned widen */
Iop_1Uto32, /* :: Ity_Bit -> Ity_I32, unsigned widen */