Enable AES, PCLMUL and RDRND for Silvermont

gcc/

2013-11-22  Yuri Rumyantsev  <ysrumyan@gmail.com>

	* config/i386/i386.c(processor_alias_table): Enable PTA_AES,
	PTA_PCLMUL and PTA_RDRND for Silvermont.
	* config/i386/driver-i386.c (host_detect_local_cpu): Set up cpu
	for Silvermont.

	* doc/invoke.texi: Mention AES, PCLMUL and RDRND for Silvermont.

libgcc/

2013-11-22  Yuri Rumyantsev  <ysrumyan@gmail.com>

	 * config/i386/cpuinfo.c (get_intel_cpu): Add Silvermont cases.

From-SVN: r205275

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4a5c9a1dc248728d56793e0d22e9da5c97640dc1..8150db9a598ed44d55a92ba1394b1663da5621e1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2013-11-22  Yuri Rumyantsev  <ysrumyan@gmail.com>
+
+       * config/i386/i386.c(processor_alias_table): Enable PTA_AES,
+       PTA_PCLMUL and PTA_RDRND for Silvermont.
+       * config/i386/driver-i386.c (host_detect_local_cpu): Set up cpu
+       for Silvermont.
+
+       * doc/invoke.texi: Mention AES, PCLMUL and RDRND for Silvermont.
+
 2013-11-22 Andrew MacLeod  <amacleod@redhat.com>
 
        * hooks.h (hook_uint_mode_0): Add Prototype.

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index a4a1f40548a28866a796e4bff037ae33dcb78cea..0b8af3f4ffd3cbbd4f0296bd871ebc74cb376f84 100644 (file)
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -646,6 +646,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
          /* Atom.  */
          cpu = "atom";
          break;
+       case 0x37:
+       case 0x4d:
+         /* Silvermont.  */
+         cpu = "slm";
+         break;
        case 0x0f:
          /* Merom.  */
        case 0x17:

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3f967e58efe5026245b055056a81bba3dec5bfa8..3c516f4359bff737dd67d5ab8dd94b6de6b0b2f6 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3147,8 +3147,8 @@ ix86_option_override_internal (bool main_args_p,
        | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
       {"slm", PROCESSOR_SLM, CPU_SLM,
        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
-       | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_MOVBE
-       | PTA_FXSR},
+       | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
+       | PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
       {"geode", PROCESSOR_GEODE, CPU_GEODE,
        PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
       {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6adfc98a22b1fb2b8ee26117e59b0e8087b395c9..7048b0bc16b28d0c6b852729d318f63638f6fbd6 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14535,7 +14535,7 @@ instruction set support.
 
 @item slm
 Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2 and POPCNT instruction set support.
+SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
 
 @item k6
 AMD K6 CPU with MMX instruction set support.

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index b5224f1989e835df3d1e9d3d63f10014b6db9693..a3521da0935b36f7e7eb41d2ccea589747d14443 100644 (file)
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,7 @@
+2013-11-22  Yuri Rumyantsev  <ysrumyan@gmail.com>
+
+        * config/i386/cpuinfo.c (get_intel_cpu): Add Silvermont cases.
+
 2013-11-18  Jan Hubicka  <jh@suse.cz>
 
        * libgcov-driver.c (run_accounted): Make global level static.

diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index 1c744f1234478ec45b53bd97b031936c97ff0b58..1a891e0c52f19a26a14317515e871cf513eea505 100644 (file)
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -170,6 +170,11 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
              /* Atom.  */
              __cpu_model.__cpu_type = INTEL_ATOM;
              break;
+           case 0x37:
+           case 0x4d:
+             /* Silvermont.  */
+             __cpu_model.__cpu_type = INTEL_SLM;
+             break;
            case 0x1a:
            case 0x1e:
            case 0x1f: