zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb \
- zynqmp-mini-qspi.dtb \
+ zynqmp-mini-qspi-parallel.dtb \
+ zynqmp-mini-qspi-single.dtb \
+ zynqmp-mini-qspi-stacked.dtb \
+ zynqmp-mini-qspi-x1-single.dtb \
+ zynqmp-mini-qspi-x1-stacked.dtb \
+ zynqmp-mini-qspi-x2-single.dtb \
+ zynqmp-mini-qspi-x2-stacked.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-emmc.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
--- /dev/null
+/*
+ * Xilinx ZynqMP QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "zynqmp-mini-qspi.dtsi"
+
+&qspi {
+ is-dual = <1>;
+ spi-rx-bus-width = <4>;
+};
--- /dev/null
+/*
+ * Xilinx ZynqMP QSPI single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "zynqmp-mini-qspi.dtsi"
+
+&qspi {
+ spi-rx-bus-width = <4>;
+};
--- /dev/null
+/*
+ * Xilinx ZynqMP QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "zynqmp-mini-qspi.dtsi"
+
+&qspi {
+ is-dual = <0>;
+ spi-rx-bus-width = <4>;
+};
--- /dev/null
+/*
+ * Xilinx ZynqMP QSPI x1 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "zynqmp-mini-qspi.dtsi"
+
+&qspi {
+ spi-rx-bus-width = <1>;
+};
--- /dev/null
+/*
+ * Xilinx ZynqMP QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "zynqmp-mini-qspi.dtsi"
+
+&qspi {
+ is-dual = <0>;
+ spi-rx-bus-width = <1>;
+};
--- /dev/null
+/*
+ * Xilinx CSE QSPI x2 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "zynqmp-mini-qspi.dtsi"
+
+&qspi {
+ spi-rx-bus-width = <2>;
+};
--- /dev/null
+/*
+ * Xilinx ZynqMP QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "zynqmp-mini-qspi.dtsi"
+
+&qspi {
+ is-dual = <0>;
+ spi-rx-bus-width = <2>;
+};
CONFIG_ZYNQMP_QSPI=y
# CONFIG_MMC is not set
CONFIG_SYS_TEXT_BASE=0xFFFC0000
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi-single"
CONFIG_SYS_EXTRA_OPTIONS="MINI_QSPI"
CONFIG_BOOTDELAY=-1
# CONFIG_DISPLAY_CPUINFO is not set