drm/i915/gtt: Revert "Disable read-only support under GVT"

This reverts commit c9e666880de5a1fed04dc412b046916d542b72dd.

Checked GVT codes that guest PPGTT PTE flag bits are propagated
to shadow PTE. Read/write bit is not changed. Further tested by
i915 self-test case "igt_ctx_readonly". No error or GPU hang was
detected. So enable read-only support under GVT.

Signed-off-by: Hang Yuan <hang.yuan@linux.intel.com>
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1540883281-11359-1-git-send-email-hang.yuan@linux.intel.com
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9ea024395d493096293c27cdfbfeee370e34e57e..a98c29147d5e9489488244bb220eba0563373f40 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1625,12 +1625,8 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
                1ULL << 48 :
                1ULL << 32;
 
-       /*
-        * From bdw, there is support for read-only pages in the PPGTT.
-        *
-        * XXX GVT is not honouring the lack of RW in the PTE bits.
-        */
-       ppgtt->vm.has_read_only = !intel_vgpu_active(i915);
+       /* From bdw, there is support for read-only pages in the PPGTT. */
+       ppgtt->vm.has_read_only = true;
 
        i915_address_space_init(&ppgtt->vm, i915);