drm/amd/pm: Delete get_dal_power_level

Not needed anymore.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index a3ee580d8dd129a2782b20483e63d17bc063da86..2cdb8fea504a0a6df35e2992df16dbeca6967fe2 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -288,7 +288,6 @@ bool dm_pp_get_clock_levels_by_type(
                DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
                validation_clks.engine_max_clock = 72000;
                validation_clks.memory_max_clock = 80000;
-               validation_clks.level = 0;
        }
 
        DRM_INFO("DM_PPLIB: Validation clocks:\n");
@@ -296,8 +295,6 @@ bool dm_pp_get_clock_levels_by_type(
                        validation_clks.engine_max_clock);
        DRM_INFO("DM_PPLIB:    memory_max_clock: %d\n",
                        validation_clks.memory_max_clock);
-       DRM_INFO("DM_PPLIB:    level           : %d\n",
-                       validation_clks.level);
 
        /* Translate 10 kHz to kHz. */
        validation_clks.engine_max_clock *= 10;

diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index 349544504c93cab0920d303f4c3a4a2f5c2aa1a3..10747a1ceda9aa8c72c4ed0e6d66d9936c632705 100644 (file)
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -113,7 +113,6 @@ struct amd_pp_display_configuration {
 struct amd_pp_simple_clock_info {
        uint32_t        engine_max_clock;
        uint32_t        memory_max_clock;
-       uint32_t        level;
 };
 
 enum PP_DAL_POWERLEVEL {

diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index 40fa2768b7727dcf6e3f7ef6b3514d2726cdd12d..ddf8822219fb8b4e572f7639098460eb60d5e61e 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1023,7 +1023,6 @@ static int pp_display_configuration_change(void *handle,
 static int pp_get_current_clocks(void *handle,
                struct amd_pp_clock_info *clocks)
 {
-       struct amd_pp_simple_clock_info simple_clocks = { 0 };
        struct pp_clock_info hw_clocks;
        struct pp_hwmgr *hwmgr = handle;
        int ret = 0;
@@ -1031,8 +1030,6 @@ static int pp_get_current_clocks(void *handle,
        if (!hwmgr || !hwmgr->pm_en)
                return -EINVAL;
 
-       phm_get_dal_power_level(hwmgr, &simple_clocks);
-
        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                                        PHM_PlatformCaps_PowerContainment))
                ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
@@ -1057,11 +1054,6 @@ static int pp_get_current_clocks(void *handle,
        clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
        clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
 
-       if (simple_clocks.level == 0)
-               clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
-       else
-               clocks->max_clocks_state = simple_clocks.level;
-
        if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
                clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
                clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
@@ -1138,8 +1130,6 @@ static int pp_get_display_mode_validation_clocks(void *handle,
        if (!hwmgr || !hwmgr->pm_en || !clocks)
                return -EINVAL;
 
-       clocks->level = PP_DAL_POWERLEVEL_7;
-
        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
                ret = phm_get_max_high_clocks(hwmgr, clocks);
 

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
index a59677cf8dfc8eb163c7bc81ecf3da43fd5df0d6..72c2d3b69a038345f4b74e7680b6981eb71b3151 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
@@ -328,16 +328,6 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
        return 0;
 }
 
-int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
-               struct amd_pp_simple_clock_info *info)
-{
-       PHM_FUNC_CHECK(hwmgr);
-
-       if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
-               return -EINVAL;
-       return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
-}
-
 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 {
        PHM_FUNC_CHECK(hwmgr);

diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h
index 915f1b8e4dbad90867c855053c97dae4c4f5fd28..36dcad065faeb6b7f06f0757e1dabab91ac925b9 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h
@@ -426,9 +426,6 @@ extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
 extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
                const struct amd_pp_display_configuration *display_config);
 
-extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
-               struct amd_pp_simple_clock_info *info);
-
 extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
 
 extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);

diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
index 1ee7e3044272d47e99de74cee5a7add0032eab84..fc1ffe1b2c97f3ed582dc03790a4323e7f28c33d 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
@@ -292,8 +292,6 @@ struct pp_hwmgr_func {
        int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
                                bool cc6_disable, bool pstate_disable,
                                bool pstate_switch_disable);
-       int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
-                       struct amd_pp_simple_clock_info *info);
        int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
                        PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
        int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,