arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity

[ Upstream commit 794d3e309e44c99158d0166b1717f297341cf3ab ]

As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/ca57409198477f7815e32a6a7467dcdc9b93dc4f.1613468366.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 5ef460458f5c374a2d03733109a7d3c17761e506..e8bf3f95c674cd3aec04a53ea7977e8a87e44567 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -153,7 +153,7 @@
 
        pmu {
                compatible = "arm,armv8-pmuv3";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 
        psci {