drm/amd/display: Remove check for DC_DMCUB_ENABLE on DCN42

[why]
DCN without DMCUB is not a supported configuration on DCN42.

[how]
Remove the DC_DMCUB_ENABLE fuse register check and remove the
corresponding entries in the DCN42 DMUB register list.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
index 7833a4fb7fbfe90e2af5b7607a0c6f139d510347..f687359b7d83bdfad9a6c5808247aad131631a1e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
@@ -321,11 +321,9 @@ void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
 
 bool dmub_dcn42_is_supported(struct dmub_srv *dmub)
 {
-       uint32_t supported = 0;
-
-       REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
-
-       return supported;
+       // DCN without DMUB is not a supported configuration; safe to assume that it is always
+       // present.
+       return true;
 }
 
 union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h
index a49d88ab0455fea76fd1af8c9234453b2160b438..c53f7691d1a8868cdf3270e1634c8d5f27993642 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h
@@ -34,7 +34,101 @@ struct dmub_srv;
 /* DCN42 register definitions. */
 
 #define DMUB_DCN42_REGS() \
-       DMUB_DCN35_REGS() \
+       DMUB_SR(DMCUB_CNTL) \
+       DMUB_SR(DMCUB_CNTL2) \
+       DMUB_SR(DMCUB_SEC_CNTL) \
+       DMUB_SR(DMCUB_INBOX0_SIZE) \
+       DMUB_SR(DMCUB_INBOX0_RPTR) \
+       DMUB_SR(DMCUB_INBOX0_WPTR) \
+       DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_INBOX1_SIZE) \
+       DMUB_SR(DMCUB_INBOX1_RPTR) \
+       DMUB_SR(DMCUB_INBOX1_WPTR) \
+       DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_OUTBOX0_SIZE) \
+       DMUB_SR(DMCUB_OUTBOX0_RPTR) \
+       DMUB_SR(DMCUB_OUTBOX0_WPTR) \
+       DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_OUTBOX1_SIZE) \
+       DMUB_SR(DMCUB_OUTBOX1_RPTR) \
+       DMUB_SR(DMCUB_OUTBOX1_WPTR) \
+       DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
+       DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
+       DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
+       DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
+       DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
+       DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
+       DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
+       DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
+       DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION4_OFFSET) \
+       DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION5_OFFSET) \
+       DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_REGION6_OFFSET) \
+       DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \
+       DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \
+       DMUB_SR(DMCUB_SCRATCH0) \
+       DMUB_SR(DMCUB_SCRATCH1) \
+       DMUB_SR(DMCUB_SCRATCH2) \
+       DMUB_SR(DMCUB_SCRATCH3) \
+       DMUB_SR(DMCUB_SCRATCH4) \
+       DMUB_SR(DMCUB_SCRATCH5) \
+       DMUB_SR(DMCUB_SCRATCH6) \
+       DMUB_SR(DMCUB_SCRATCH7) \
+       DMUB_SR(DMCUB_SCRATCH8) \
+       DMUB_SR(DMCUB_SCRATCH9) \
+       DMUB_SR(DMCUB_SCRATCH10) \
+       DMUB_SR(DMCUB_SCRATCH11) \
+       DMUB_SR(DMCUB_SCRATCH12) \
+       DMUB_SR(DMCUB_SCRATCH13) \
+       DMUB_SR(DMCUB_SCRATCH14) \
+       DMUB_SR(DMCUB_SCRATCH15) \
+       DMUB_SR(DMCUB_SCRATCH16) \
+       DMUB_SR(DMCUB_SCRATCH17) \
+       DMUB_SR(DMCUB_SCRATCH18) \
+       DMUB_SR(DMCUB_SCRATCH19) \
+       DMUB_SR(DMCUB_SCRATCH20) \
+       DMUB_SR(DMCUB_SCRATCH21) \
+       DMUB_SR(DMCUB_GPINT_DATAIN0) \
+       DMUB_SR(DMCUB_GPINT_DATAIN1) \
+       DMUB_SR(DMCUB_GPINT_DATAOUT) \
+       DMUB_SR(MMHUBBUB_SOFT_RESET) \
+       DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
+       DMUB_SR(DCN_VM_FB_OFFSET) \
+       DMUB_SR(DMCUB_TIMER_CURRENT) \
+       DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
+       DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
+       DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
+       DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \
+       DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
+       DMUB_SR(DMCUB_INTERRUPT_ACK) \
+       DMUB_SR(DMU_CLK_CNTL) \
        DMUB_SR(DMCUB_INTERRUPT_STATUS) \
        DMUB_SR(DMCUB_REG_INBOX0_RDY) \
        DMUB_SR(DMCUB_REG_INBOX0_MSG0) \
@@ -59,7 +153,45 @@ struct dmub_srv;
        DMUB_SR(HOST_INTERRUPT_CSR)
 
 #define DMUB_DCN42_FIELDS() \
-       DMUB_DCN35_FIELDS() \
+       DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
+       DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
+       DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
+       DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
+       DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
+       DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
+       DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
+       DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
+       DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
+       DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
+       DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
+       DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
+       DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
+       DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
+       DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
+       DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
+       DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_TOP_ADDRESS) \
+       DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_ENABLE) \
+       DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
+       DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
+       DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
+       DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
+       DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \
+       DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \
+       DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \
+       DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS) \
+       DMUB_SF(DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE) \
+       DMUB_SF(DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE) \
+       DMUB_SF(DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE) \
        DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \
        DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \
        DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \