]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amdgpu: Add kiq hdp flush callbacks
authorVictor Zhao <Victor.Zhao@amd.com>
Thu, 9 Oct 2025 02:38:28 +0000 (10:38 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 20 Oct 2025 22:25:36 +0000 (18:25 -0400)
Add kiq hdp flush callbacks for gfx ips to support gpu hdp flush when no
ring presents

Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

index 8841d7213de456e4bf03113d1abef096a2f3cd21..751732f3e8839ee3622d597b46f35745485e682e 100644 (file)
@@ -9951,6 +9951,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
        .emit_wreg = gfx_v10_0_ring_emit_wreg,
        .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
+       .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
 };
 
 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
index d61eb9f187c649c21f594f7bead9656cdb8c77e5..252517ce5d5af41b645232f047eaef086d43aa87 100644 (file)
@@ -2438,7 +2438,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
                        if (version_minor == 3)
                                gfx_v11_0_load_rlcp_rlcv_microcode(adev);
                }
-               
+
                return 0;
        }
 
@@ -3886,7 +3886,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
        }
 
        memcpy(fw, fw_data, fw_size);
-       
+
        amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
        amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 
@@ -7318,6 +7318,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
        .emit_wreg = gfx_v11_0_ring_emit_wreg,
        .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
+       .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
 };
 
 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev)
index 93fde0f9af87f8446037a3b52b40ea57b071dbd0..35d5a7e99a7c67b032a18db59c741180aab53713 100644 (file)
@@ -5595,6 +5595,7 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {
        .emit_wreg = gfx_v12_0_ring_emit_wreg,
        .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
+       .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
 };
 
 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev)
index 0856ff65288c0e588595f61e352e50c4f62f9426..d3d0a4b0380cfab5cabeef2d03036757863fb9a0 100644 (file)
@@ -6939,6 +6939,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
        .pad_ib = amdgpu_ring_generic_pad_ib,
        .emit_rreg = gfx_v8_0_ring_emit_rreg,
        .emit_wreg = gfx_v8_0_ring_emit_wreg,
+       .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
 };
 
 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
index dd19a97436db95960fb30e4a5af9c9e0a83da74c..f1a2efc2a8d0a4e2c9c969a5cc58ea41f5fe18cc 100644 (file)
@@ -7586,6 +7586,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
        .emit_wreg = gfx_v9_0_ring_emit_wreg,
        .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
+       .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
 };
 
 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
index fb5585ab52beb0b1ce280c5ebd072ed5d01f48f5..e0b50c690f8cb9605f70b4b0361b9cd392316ab6 100644 (file)
@@ -4792,6 +4792,7 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {
        .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
        .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
+       .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,
 };
 
 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev)