KVM: arm64: Remove @arch from __load_stage2()

Since commit fe49fd940e22 ("KVM: arm64: Move VTCR_EL2 into struct s2_mmu"),
@arch is no longer required to obtain the per-kvm_s2_mmu vtcr and can be
removed from __load_stage2().

Signed-off-by: Zenghui Yu (Huawei) <zenghui.yu@linux.dev>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://patch.msgid.link/20260318144305.56831-1-zenghui.yu@linux.dev
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 01e9c72d6aa7a67f0a470ec6f8e916de9facf195..6eae7e7e2a68450100e30990bafe73e2310d6ea3 100644 (file)
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -318,8 +318,7 @@ static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu)
  * Must be called from hyp code running at EL2 with an updated VTTBR
  * and interrupts disabled.
  */
-static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu,
-                                         struct kvm_arch *arch)
+static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu)
 {
        write_sysreg(mmu->vtcr, vtcr_el2);
        write_sysreg(kvm_get_vttbr(mmu), vttbr_el2);

diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c
index 9f8f0ae8e86e84c3e36f6b77d6b06f7bd3a8d2b6..b91ef006919e0459bbf6c6e6ad639e940d102a2d 100644 (file)
--- a/arch/arm64/kvm/at.c
+++ b/arch/arm64/kvm/at.c
@@ -1380,7 +1380,7 @@ static u64 __kvm_at_s1e01_fast(struct kvm_vcpu *vcpu, u32 op, u64 vaddr)
                }
        }
        write_sysreg_el1(vcpu_read_sys_reg(vcpu, SCTLR_EL1),    SYS_SCTLR);
-       __load_stage2(mmu, mmu->arch);
+       __load_stage2(mmu);
 
 skip_mmu_switch:
        /* Temporarily switch back to guest context */

diff --git a/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h b/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
index 3cbfae0e3dda13c5f802629de5545b0d4a6f37a7..aaeec6862215e47181782192be096f1e253d5043 100644 (file)
--- a/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/mem_protect.h
@@ -67,7 +67,7 @@ int refill_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages,
 static __always_inline void __load_host_stage2(void)
 {
        if (static_branch_likely(&kvm_protected_mode_initialized))
-               __load_stage2(&host_mmu.arch.mmu, &host_mmu.arch);
+               __load_stage2(&host_mmu.arch.mmu);
        else
                write_sysreg(0, vttbr_el2);
 }

diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
index 28a471d1927cd50f908ea0dc14b8f583700d1cd8..888bd7e71d0c39fd02905fee23064d8e4a0e2573 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
+++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
@@ -337,7 +337,7 @@ int __pkvm_prot_finalize(void)
        kvm_flush_dcache_to_poc(params, sizeof(*params));
 
        write_sysreg_hcr(params->hcr_el2);
-       __load_stage2(&host_mmu.arch.mmu, &host_mmu.arch);
+       __load_stage2(&host_mmu.arch.mmu);
 
        /*
         * Make sure to have an ISB before the TLB maintenance below but only

diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c
index 8d1df3d33595bdc6366fd0747da8f08dae57106a..7318e3e6a5f3648d0a8d9ae978855594c6d61088 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/switch.c
+++ b/arch/arm64/kvm/hyp/nvhe/switch.c
@@ -315,7 +315,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
        __sysreg_restore_state_nvhe(guest_ctxt);
 
        mmu = kern_hyp_va(vcpu->arch.hw_mmu);
-       __load_stage2(mmu, kern_hyp_va(mmu->arch));
+       __load_stage2(mmu);
        __activate_traps(vcpu);
 
        __hyp_vgic_restore_state(vcpu);

diff --git a/arch/arm64/kvm/hyp/nvhe/tlb.c b/arch/arm64/kvm/hyp/nvhe/tlb.c
index b29140995d484a66ebb2b5574b406bf57be46c21..fdb90483340cea769eaa9910522e88b7c8db69d1 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/tlb.c
+++ b/arch/arm64/kvm/hyp/nvhe/tlb.c
@@ -110,7 +110,7 @@ static void enter_vmid_context(struct kvm_s2_mmu *mmu,
        if (vcpu)
                __load_host_stage2();
        else
-               __load_stage2(mmu, kern_hyp_va(mmu->arch));
+               __load_stage2(mmu);
 
        asm(ALTERNATIVE("isb", "nop", ARM64_WORKAROUND_SPECULATIVE_AT));
 }
@@ -128,7 +128,7 @@ static void exit_vmid_context(struct tlb_inv_context *cxt)
                return;
 
        if (vcpu)
-               __load_stage2(mmu, kern_hyp_va(mmu->arch));
+               __load_stage2(mmu);
        else
                __load_host_stage2();
 

diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
index 1e8995add14fa32d38cf9271f41967f3338d5e9d..bbe9cebd3d9d578bac802fe71a7566fe3dab3f81 100644 (file)
--- a/arch/arm64/kvm/hyp/vhe/switch.c
+++ b/arch/arm64/kvm/hyp/vhe/switch.c
@@ -219,7 +219,7 @@ void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu)
 
        __vcpu_load_switch_sysregs(vcpu);
        __vcpu_load_activate_traps(vcpu);
-       __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch);
+       __load_stage2(vcpu->arch.hw_mmu);
 }
 
 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu)

diff --git a/arch/arm64/kvm/hyp/vhe/tlb.c b/arch/arm64/kvm/hyp/vhe/tlb.c
index f7b9dfe3f3a5a9193423bf471181a7aa0db774a8..c386d9f1c101614c53dc5140a0b197c0968fb891 100644 (file)
--- a/arch/arm64/kvm/hyp/vhe/tlb.c
+++ b/arch/arm64/kvm/hyp/vhe/tlb.c
@@ -60,7 +60,7 @@ static void enter_vmid_context(struct kvm_s2_mmu *mmu,
         * place before clearing TGE. __load_stage2() already
         * has an ISB in order to deal with this.
         */
-       __load_stage2(mmu, mmu->arch);
+       __load_stage2(mmu);
        val = read_sysreg(hcr_el2);
        val &= ~HCR_TGE;
        write_sysreg_hcr(val);
@@ -78,7 +78,7 @@ static void exit_vmid_context(struct tlb_inv_context *cxt)
 
        /* ... and the stage-2 MMU context that we switched away from */
        if (cxt->mmu)
-               __load_stage2(cxt->mmu, cxt->mmu->arch);
+               __load_stage2(cxt->mmu);
 
        if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
                /* Restore the registers to what they were */