re PR target/59844 (Powerpc64le cannot bootstrap with -O3/-mcpu=power8)

2014-01-16  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/59844
	* config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little
	endian support, remove tests for WORDS_BIG_ENDIAN.
	(p8_mfvsrd_3_<mode>): Likewise.
	(reload_gpr_from_vsx<mode>): Likewise.
	(reload_gpr_from_vsxsf): Likewise.
	(p8_mfvsrd_4_disf): Likewise.

From-SVN: r206668

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7d57619b071bfaabac9889ac4a15f9c4c40d644e..1f17de0ec2802d1d268c68791aa2997990b7eee7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2014-01-16  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/59844
+       * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little
+       endian support, remove tests for WORDS_BIG_ENDIAN.
+       (p8_mfvsrd_3_<mode>): Likewise.
+       (reload_gpr_from_vsx<mode>): Likewise.
+       (reload_gpr_from_vsxsf): Likewise.
+       (p8_mfvsrd_4_disf): Likewise.
+
 2014-01-16  Richard Biener  <rguenther@suse.de>
 
        PR rtl-optimization/46590

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 744a11d6d96986c798f9cef9a16b2e71066247f7..726b3b09edcb785b139676ae206c76bba3974e17 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -9972,7 +9972,7 @@
        (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
                   UNSPEC_P8V_RELOAD_FROM_GPR))
    (clobber (match_operand:DI 2 "register_operand" "=r"))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -9999,7 +9999,7 @@
   [(set (match_operand:DF 0 "register_operand" "=r")
        (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
                   UNSPEC_P8V_RELOAD_FROM_VSX))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "mfvsrd %0,%x1"
   [(set_attr "type" "mftgpr")])
 
@@ -10009,7 +10009,7 @@
         [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
         UNSPEC_P8V_RELOAD_FROM_VSX))
    (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -10036,7 +10036,7 @@
        (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
                   UNSPEC_P8V_RELOAD_FROM_VSX))
    (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -10058,7 +10058,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
                   UNSPEC_P8V_RELOAD_FROM_VSX))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "mfvsrd %0,%x1"
   [(set_attr "type" "mftgpr")])