zynq: rsa: Added RSA-AES for the zynq board

Added RSA-AES support for the zynq boards with
config rsa as config option.Added autoboot support
if built for zynq with config rsa config option.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/boards.cfg b/boards.cfg
index ea4f354f5f005b5541ccfe3cf1819c1365342baa..6766e9e2c51dac909a073c545dbb41f83d10c1e5 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -356,6 +356,15 @@ Active  arm         armv7          zynq        xilinx          zynq
 Active  arm         armv7          zynq        xilinx          zynq                zynq_cse_qspi                        zynq_cse:CSE_QSPI                                                                                                                 Michal Simek <michal.simek@xilinx.com>
 Active  arm         armv7          zynq        xilinx          zynq                zynq_cse_nand                        zynq_cse:CSE_NAND                                                                                                                 Michal Simek <michal.simek@xilinx.com>
 Active  arm         armv7          zynq        xilinx          zynq                zynq_cc108                           -                                                                                                                                 Michal Simek <michal.simek@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM010_RSA                 zynq_zc770:ZC770_XM010,CMD_ZYNQ_RSA                                                                                                   Michal Simek <michal.simek@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM011_RSA                 zynq_zc770:ZC770_XM011,CMD_ZYNQ_RSA                                                                                                   Michal Simek <michal.simek@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM012_RSA                 zynq_zc770:ZC770_XM012,CMD_ZYNQ_RSA                                                                                                   Michal Simek <michal.simek@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM013_RSA                 zynq_zc770:ZC770_XM013,CMD_ZYNQ_RSA                                                                                                   Michal Simek <michal.simek@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_afx_nor_RSA                     zynq_afx:AFX_NOR,CMD_ZYNQ_RSA                                                                                                         Michal Simek <michal.simek@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_afx_qspi_RSA                    zynq_afx:AFX_QSPI,CMD_ZYNQ_RSA                                                                                                        Michal Simek <michal.simek@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_afx_nand_RSA                    zynq_afx:AFX_NAND,CMD_ZYNQ_RSA                                                                                                        Michal Simek <michal.simek@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zc70x_RSA                       zynq_zc70x:CMD_ZYNQ_RSA                                                                                                               Michal Simek <michal.simek@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zed_RSA                         zynq_zed:CMD_ZYNQ_RSA                                                                                                                 Michal Simek <michal.simek@xilinx.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>

diff --git a/include/configs/zynq_common.h b/include/configs/zynq_common.h
index 77082d6d41bc7cf10851e10d8d47274867946dc8..2acf3ee3d43152ab614306e5370f9fb7c6fc3030 100644 (file)
--- a/include/configs/zynq_common.h
+++ b/include/configs/zynq_common.h
@@ -45,6 +45,11 @@
 #define CONFIG_ZYNQ_SERIAL
 #endif
 
+#if defined(CONFIG_CMD_ZYNQ_RSA)
+#define CONFIG_SHA256
+#define CONFIG_CMD_ZYNQ_AES
+#endif
+
 /* DCC driver */
 #if defined(CONFIG_ZYNQ_DCC)
 # define CONFIG_ARM_DCC
@@ -209,11 +214,13 @@
        "ramdisk_image=uramdisk.image.gz\0"     \
        "devicetree_image=devicetree.dtb\0"     \
        "bitstream_image=system.bit.bin\0"      \
+       "boot_image=BOOT.bin\0" \
        "loadbit_addr=0x100000\0"       \
        "loadbootenv_addr=0x2000000\0" \
        "kernel_size=0x500000\0"        \
        "devicetree_size=0x20000\0"     \
        "ramdisk_size=0x5E0000\0"       \
+       "boot_size=0xF00000\0"  \
        "fdt_high=0x20000000\0" \
        "initrd_high=0x20000000\0"      \
        "bootenv=uEnv.txt\0" \
@@ -264,10 +271,35 @@
                "tftp 0x3000000 ${kernel_image} && " \
                "tftp 0x2A00000 ${devicetree_image} && " \
                "tftp 0x2000000 ${ramdisk_image} && " \
+               "bootm 0x3000000 0x2000000 0x2A00000\0" \
+       "rsa_norboot=echo Copying Image from NOR flash to RAM... && " \
+               "cp.b 0xE2100000 0x100000 ${boot_size} && " \
+               "zynqrsa 0x100000 && " \
+               "bootm 0x3000000 0x2000000 0x2A00000\0" \
+       "rsa_nandboot=echo Copying Image from NAND flash to RAM... && " \
+               "nand read 0x100000 0x0 ${boot_size} && " \
+               "zynqrsa 0x100000 && " \
+               "bootm 0x3000000 0x2000000 0x2A00000\0" \
+       "rsa_qspiboot=echo Copying Image from QSPI flash to RAM... && " \
+               "sf probe 0 0 0 && " \
+               "sf read 0x100000 0x0 ${boot_size} && " \
+               "zynqrsa 0x100000 && " \
+               "bootm 0x3000000 0x2000000 0x2A00000\0" \
+       "rsa_sdboot=echo Copying Image from SD to RAM... && " \
+               "fatload mmc 0 0x100000 ${boot_image} && " \
+               "zynqrsa 0x100000 && " \
+               "bootm 0x3000000 0x2000000 0x2A00000\0" \
+       "rsa_jtagboot=echo TFTPing Image to RAM... && " \
+               "tftp 0x100000 ${boot_image} && " \
+               "zynqrsa 0x100000 && " \
                "bootm 0x3000000 0x2000000 0x2A00000\0"
 
 /* default boot is according to the bootmode switch settings */
+#if defined(CONFIG_CMD_ZYNQ_RSA)
+#define CONFIG_BOOTCOMMAND             "run rsa_$modeboot"
+#else
 #define CONFIG_BOOTCOMMAND             "run $modeboot"
+#endif
 #define CONFIG_BOOTDELAY               3 /* -1 to Disable autoboot */
 #define CONFIG_SYS_LOAD_ADDR           0 /* default? */