--- /dev/null
+From 009bdd7a91990982e5b3bab4001318dfe5f6f575 Mon Sep 17 00:00:00 2001
+From: George Moussalem <george.moussalem@outlook.com>
+Date: Sun, 07 Jun 2026 13:00:06 +0400
+Subject: [PATCH v4 1/4] dt-bindings: net: ethernet-phy: increase max clock count to two
+MIME-Version: 1.0
+Content-Type: text/plain; charset="utf-8"
+Content-Transfer-Encoding: 7bit
+Message-Id: <20260607-ipq5018-gephy-clocks-v4-1-15b3a5ba7460@outlook.com>
+
+The clocks property has a restriction to maximum one.
+Yet, some PHYs may require more than 1 clock such as the IPQ5018 PHY
+which requires two clocks for RX and TX. As such, increase maxItems to
+two.
+
+Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
+Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+---
+Commit 350b7a258f20 introduced the clocks property with a restriction to
+maximum 1 to the main ethernet-phy.yaml binding for Realtek to add an
+optional external clock source. This is restrictive to all PHY bindings,
+as some PHYs may require more than 1 clock such as the IPQ5018 PHY which
+requires 2 clocks (for RX and TX).
+---
+ Documentation/devicetree/bindings/net/ethernet-phy.yaml | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml
++++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
+@@ -102,10 +102,13 @@ properties:
+ by software.
+
+ clocks:
+- maxItems: 1
++ minItems: 1
++ maxItems: 2
+ description:
+- External clock connected to the PHY. If not specified it is assumed
+- that the PHY uses a fixed crystal or an internal oscillator.
++ External clock connected to the PHY or RX and TX clocks that the PHY
++ requires to enable explicitly. If not specified it is assumed
++ that the PHY uses a fixed crystal or an internal oscillator or that the
++ RX/TX clocks are hardware enabled by default.
+
+ enet-phy-lane-swap:
+ $ref: /schemas/types.yaml#/definitions/flag
--- /dev/null
+From ea59840c0b6839c65eaf39887a0762dfc4993f50 Mon Sep 17 00:00:00 2001
+From: George Moussalem <george.moussalem@outlook.com>
+Date: Sun, 07 Jun 2026 13:00:08 +0400
+Subject: [PATCH v4 3/4] arm64: qcom: ipq5018: Add GEPHY RX and TX clocks
+MIME-Version: 1.0
+Content-Type: text/plain; charset="utf-8"
+Content-Transfer-Encoding: 7bit
+Message-Id: <20260607-ipq5018-gephy-clocks-v4-3-15b3a5ba7460@outlook.com>
+
+Add RX and TX clocks for the IPQ5018 GEPHY to enable the datapath.
+
+Fixes: f5f2b835e316 ("arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus")
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+---
+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+@@ -234,6 +234,9 @@
+ compatible = "ethernet-phy-id004d.d0c0";
+ reg = <7>;
+
++ clocks = <&gcc GCC_GEPHY_RX_CLK>,
++ <&gcc GCC_GEPHY_TX_CLK>;
++ clock-names = "rx", "tx";
+ resets = <&gcc GCC_GEPHY_MISC_ARES>;
+ };
+ };
--- /dev/null
+From 929c734775fc0e4f576727b47f8a07d7e5cabb4f Mon Sep 17 00:00:00 2001
+From: George Moussalem <george.moussalem@outlook.com>
+Date: Sun, 07 Jun 2026 13:00:09 +0400
+Subject: [PATCH v4 4/4] net: phy: at803x: add RX and TX clock management for IPQ5018 PHY
+MIME-Version: 1.0
+Content-Type: text/plain; charset="utf-8"
+Content-Transfer-Encoding: 7bit
+Message-Id: <20260607-ipq5018-gephy-clocks-v4-4-15b3a5ba7460@outlook.com>
+
+Acquire and enable the RX and TX clocks for the IPQ5018 PHY.
+These clocks are required for the PHY's datapath to function correctly.
+
+Fixes: d46502279a11 ("net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support")
+Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+---
+ drivers/net/phy/qcom/at803x.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -19,6 +19,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/of.h>
+ #include <linux/phylink.h>
++#include <linux/clk.h>
+ #include <linux/reset.h>
+ #include <linux/sfp.h>
+ #include <dt-bindings/net/qca-ar803x.h>
+@@ -176,6 +177,8 @@ struct at803x_context {
+ };
+
+ struct ipq5018_priv {
++ struct clk *rx_clk;
++ struct clk *tx_clk;
+ struct reset_control *rst;
+ bool set_short_cable_dac;
+ };
+@@ -1099,6 +1102,16 @@ static int ipq5018_probe(struct phy_devi
+ priv->set_short_cable_dac = of_property_read_bool(dev->of_node,
+ "qcom,dac-preset-short-cable");
+
++ priv->rx_clk = devm_clk_get_enabled(dev, "rx");
++ if (IS_ERR(priv->rx_clk))
++ return dev_err_probe(dev, PTR_ERR(priv->rx_clk),
++ "failed to get and enable RX clock\n");
++
++ priv->tx_clk = devm_clk_get_enabled(dev, "tx");
++ if (IS_ERR(priv->tx_clk))
++ return dev_err_probe(dev, PTR_ERR(priv->tx_clk),
++ "failed to get and enable TX clock\n");
++
+ priv->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(priv->rst))
+ return dev_err_probe(dev, PTR_ERR(priv->rst),
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -736,6 +736,118 @@
+@@ -739,6 +739,118 @@
};
};
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -266,7 +266,7 @@
+@@ -269,7 +269,7 @@
"sys";
#clock-cells = <1>;
assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
projects / thirdparty / openwrt.git / commitdiff
